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TC9349AFG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9349AFG
Single-Chip DTS Microcontroller (DTS-21)
The TC9349AFG is a single-chip DTS microcontroller for portable audio incorporating a 30 MHz prescaler, PLL, and LCD driver. In addition to an IF counter, serial interface and buzzer function, the device incorporates an interrupt function, timer counter, pulse counter, electronic volume function and A/D converter The device also supports selection of 1/4-duty 1/2 bias or 1/4-duty 1/3 bias for the LCD driver, while a built-in 3 V voltage doubler boosting circuit implements stable operation of the LCD monitor. The power supply voltage ranges from 0.9 V to 1.8 V. Due to its low-current consumption, the device is suitable for use in digital tuning systems in portable equipment such as headphone stereos.
Weight: 0.32 g (typ.)
Features
* * * * * * * * * CMOS DTS microcontroller LSI with built-in prescaler PLL and LCD driver Operating voltage range: Current dissipation: Operating temperature range: Program memory (ROM): Data memory (RAM): Oscillator frequency: Instruction execution time: Interrupt: VDD = 0.9 to 1.8 V (typ.: 1.5 V) With CPU in operation: IDD = 150 A (typ.) With PLL in operation: IDD = 1 mA (typ. At inputting OSCin = 30 MHz) Ta = -10 to 60C 16-bit x 8192 steps 4-bit x 512 words Crystal oscillator: 75 kHz (crystal oscillator) High-speed oscillator: 300 to 600 kHz (ceramic oscillator or crystal oscillator) Crystal oscillator: 40 s High-speed oscillator: 5 to 10 s External: Internal: * * * Interrupt stack: Address stack: I/O port: 2 system (INTR1, INTR2 pin) 4 system (serial-interface, timer-port, timer-counter, decreased voltage detection)
4 level x 26 bit G-register, Data select, Carry flag, Data register 16 level x 13 bit (program counter) CMOS I/O port: 36 (max) N-ch open-drain I/O port: 9 (max) Exclusive output port: 2 (max), exclusive input port: 1 (max) 1/4 duty, 1/2 bias or 1/4 duty, 1/3 bias: 72 segments (max) 1 system, 2 channel (N-ch open-drain, CMOS I/O port), 3 kinds (3-wired, 2-wired, UART) 4 kinds of frequency (1 kHz, 1.56 kHz, 2.08 kHz, 3 kHz), 4 modes (continuous, single-shot, 10 Hz intermittent, 10 Hz intermittent 1 Hz interval) 8 bit, 2 kinds of timer clock (25 kHz, 1 kHz), 2 modes (timer counter, pulse width measure (INTR1 pin)) 8 bit up/down counter 2 channel, 32 step (0 dB to -78 dB, -dB) 6 bit, 4 channel, conversion time: 240 s 5.5 V output max. (Tout, Tin) 2 stage (0.75 V, 1.0 V) voltage detected (VDET) 15 kinds of doubler clock, 2 types of doubler clock output (CMOS output: DDCK2, N-ch output: DDCK1)
* * * * * * * * *
LCD driver: Serial Interface: Buzzer: Timer counter: Pulse counter: Electronic volume: A/D converter: Amplifier for LPF: DC/DC converter of VT:
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* DC/DC converter for CPU: Charge-pump type Two kinds of doubler clock: 75 kHz crystal oscillator, high-speed oscillator clock (300 to 600 kHz), setting doubler voltage for 3 stages (2.0 V, 2.5 V, 3.0 V) 16-bit HF mode: 1/15 or 16-pulse swallow-type (1 to 30 MHz, Vin = 0.1Vp-p (min)) LF mode: 12 bit direct divider type (0.5 to 4 MHz, Vin = 0.1Vp-p (min)) 10 kinds (1 kHz, 1.3889 kHz, 1.5625 kHz, 2.7778 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25 kHz, 12.5 kHz, 25 kHz) 2 (max), setting for "H"/"L" level, High-impedance and built-in output resistor by program. two units (max); "H"/"L" level-setting, high-impedance setting, and built-in output resistor setting (0 k, 5 k, 50 k, 100 k) possible through programming (DO1/DO2); automatic change of output resistor according to phase difference is possible through programming. (DO2) 20 bits, 0.03 to 12 MHz, Vin = 0.1Vp-p (min) three modes: clock stop (stoppage of crystal oscillator); hard wait, (crystal oscillator operation only); soft wait (CPU intermittent operation) Built-in power-on reset circuit
* * *
Programmable counter: Reference frequency: Phase comparator:
* * * * * *
General-purpose IF counter: Backup function: Reset function:
Decreased voltage detection function: Voltage detection is possible in 25 mV steps in the range VDD = 0.850 V to 1.225 V. Decreased voltage detection enables selection of the CPU stop function. Package: EEPROM product: QFP-64 (0.5 mm in pitch, 1.4 mm thick) TC93E49FG
Note:
This product is sensitive to electrostatic discharge. Handle with care.
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Pin Assignment
P3-1/SDIO1/TX1 (BRK2) P4-1/INTR2/INH (BRK6) P3-0/SCK1/RX1 (BRK1)
P3-3/PCTRin (BRK4)
P4-3/VRout1 (BRK8)
P4-0/INTR1 (BRK5)
P4-2/BUZR (BRK7)
P16-3/S18/Xout2
P3-2/SI1 (BRK3)
P16-2/S17/Xin2
P5-3/VRout2
P5-1/VRcom
P5-0/VRin1
P5-2/VRin2
P16-1/S16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
IFin/IN VPLL OSCin GND (PLL) DO1/OT1/P DO2/OT2/N/Tin P9-0/Tout MUTE/P9-1 P9-2/DDCK2/TEST P8-0/VDET (BRK13) P8-1/SI2/DDCK1 (BRK14) P8-2/SCK2/RX2 (BRK15) P8-3/SDIO2/TX2 (BRK16)
RESET GND Xin1
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Electronic volume
SIO1 Pull-up/pull-down
P16-0/S15
32 31 LCD driver (1/4 duty, 1/3 or 1/2 bias: 72 segments max) 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P15-1/S14 P15-0/S13 P14-3/S12 P14-2/S11 P14-1/S10 P14-0/S9 P13-3/S8 P13-2/S7 P13-1/S6 P13-0/S5 P12-3/S4 P12-2/S3 P12-1/S2 P12-0/S1 P10-3/COM4 P10-2/COM3
CMOS I/O port (34)
PLL
N-ch open drain I/O port (1) CMOSI/O port (2) SVFP64 (0.5 mm pitch) Top - view
N-ch open drain I/O port (4)
SIO2
Oscillation 64 circuit 1 2 3
N-ch open drain I/O port (4) Doubler/regular circuit 4 5 6 7 8 9 A/D (4ch)
10 11 12 13 14 15 16
VDD
VDB
VEE
Xout1
VCPU
VLCD
C1
C2
C3
C4
P10-0/COM1
P6-1/ADin2 (BRK10)
P6-2/ADin3 (BRK11)
P6-3/ADin4 (BRK12)
P6-0/ADin1 (BRK9)
P10-1/COM2
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Block Diagram
VDD VLCD
MUTE G-Reg. MUTE VDD VLCD RAM (4 x 512 Words) P8-0/VDET (BRK13) P8-1/SI2/DDCK1 (BRK14) P8-2/SCK2/RX2 (BRK15) P8-3/SDIO2/TX2 (BRK16)
ALU A/D Conv. R/WBuf. Port 6
P6-3/ADin4 (BRK12) P6-2/ADin3 (BRK11) P6-1/ADin4 (BRK10) P6-0/ADin4 (BRK9)
Port 8 Interrupt Stack Reg. (4 Levels) DDCK1 VDET DDCK Data Select
Ca
VEE
VDB
VLCD
VCPU
DDCK Control DDCK2 MUTE VEE VDB
VR
Data Reg (16 bits)
P5-3/VRout2 P5-2/VRin2 P5-1/VRcom P5-0/VRin1
P9-0/Tout MUTE/P9-1 P9-2/DDCK2/TEST
Port 9 ROM (16 x 8192 Steps) VDD VLCD
Instruction Decoder
Port 5
BUZR Port 4
P4-3/VRout1 (BRK8) P4-2/BUZR (BRL7) P4-1/INTR2/ INH (BRK6) P4-0/INTR1 (BRK5)
IFin/IN
IF Counter DDCK
VDB Program Counter
Interrupt Control
VPLL OSCin GND
Timer
VDD VDD
VLCD VLCD
PLL
Address Stack Reg. (16 Levels) Up/Down Counter Port 3 Serial Interface
DO1/OT1/P DO2/OT2/NTin
Phase Comp.
P3-3/PCTRin (BRK4) P3-2/S11 (BRL3) P3-1/SDIO/TX1 (BRK2) P3-0/SCK1/RX1 (BRK1)
VDB Reset
OSC Control CPU Clock
RESET
Reset
GND
Xin1 Xout1 VDD C1 C2 VDB OSC2 Doubler OSC2 OSC1 OSC2 Peripheral VDD
VEE C3 C4 VLCD
VEE (1.5 V) Doubler
VDD
VLCD
LCD Driver
Port 10 Port 12 Port 13 Port 14 Port 15
Port 16
VLCD
VDB
P10-0/COM1
P10-3/COM4
P12-0/S1
P12-3/S4
P13-0/S5
P13-3/S8
P14-0/S9
P14-3/S12
P15-0/S13
P15-1/S14
: N-ch Open drain
P16-0/S15 P16-1/S16 P16-2/S17/Xin2 P16-3/S18/Xout2
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Description of Pin Functions
PIN No. Symbol Pin Name Function and Operation Remarks
Xout1
64 Xin1 Crystal oscillator pins. A reference 75 kHz crystal resonator is connected to the Xin1 and Xout1 pins.
Rout1 RfXT1 VDD
Crystal oscillator pin
Xin1
1
Xout1
(Xin1, Xout1)
68
GND
Power-supply pins
Power supply pin for the crystal oscillator and doubler circuit for the CPU (VDB). Normally, VDD = 0.9 to 1.8 V is applied. VDD potential is detected in the 0.850 V to 1.225 V range in 25 mV steps using the decreased voltage detection circuit. If VDD potential falls below the voltage being set, the CPU can be stopped to prevent incorrect operation. Note: After reset, the voltage set for the decreased voltage detection is VDD = 0.85 V. CPU stop function is enabled.
GND
2
VDD
VDD
Doubler output pins for CPU. The doubler system is the charge-pump system. When a doubler clamp is permitted, a voltage of 2.0 V, 2.5 V or 3.0 V can be selected. A doubler clock can select either one of 75 kHz, 37.5 kHz or high-speed oscillator clock. Usually, the VDB pin connected to the capacitor for stabilization (0.1 F, 10 F typ.) supplies voltage for the power supply of the CPU only ( VCPU). The VDB potential is supplied to the power supply of the A/D converter, and a 1.5 V constant-voltage circuit ( VEE). The voltage is doubled by the doubler capacitor between C1 and C2 (0.47 F typ.). When the doubler clamp is enabled, the voltage is doubled below the voltage being set. 5 VDB Note: During reset or execution of the clock stop instruction, the VDB pin is set to VDD level. The LX pin is L level for CMOS output, and at high impedance for open-drain output.
3
C1
4
C2
Doubler output pins for CPU
VDB
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PIN No. Symbol Pin Name Function and Operation Remarks
6
C3
7
C4
Doubler output pin for LCD driver
Doubler output pin for the LCD driver. The VLCD pin doubles the VEE pin voltage to 3 V using the voltage doubler capacitance between C3 and C4. The doubled VLCD voltage is supplied to the I/O port, the power supply of the LCD driver, and the electronic volume power supply. Usually, the stabilizing capacitor (0.1 F typ.) is connected between the VLCD pin and GND. The voltage doubler capacitor (0.1 F typ.) is connected between C3 and C4. Note: During reset or execution of a clock stop instruction, the VLCD pin is set to the VCPU power supply level.
VLCD
8
VLCD
9
VEE
Constant-voltage output pin. The VEE pin outputs 1.5 V (typ.) constant-voltage power supply. The VEE potential is used for the voltage doubler for the CPU, the clamp function of Constant-voltage output the DC/DC converter and the reference voltage of the A/D converter. pin The stabilizing capacitor (0.47 F typ.) is connected to the VEE pin. Note: During reset or execution of the clock stop instruction, the VEE pin is at high impedance. CPU power supply pin. Normally, 1.2 to 3.6 V is applied. When memory backup is required, VDB potential is applied to this pin and this pin's potential is held. In backup state (at execution of the CKSTP instruction), current dissipation drops (0.5 A or less), and the power supply voltage can be reduced to 0.75 V. If voltage is applied to this pin, the device system is reset and the program starts from address "0" (power-on reset). Note: To operate the power-on reset, the power supply should start up in 10 to 100 ms. Note: To be used with VCPU VLCD. 4-bit N-ch open-drain I/O ports, allowing input and output to be programmed in 1-bit units. If the ports are set as the input state of an I/O port, these can be set to break pins. The backup mode can be released by changing the input state of the break pin in the backup mode. I/O ports are N-ch open-drain output. Up to the VDB voltage can be applied to the AD input pins. Pins P6-0 to P6-3 can also be used for analog input to the built-in 6-bit, 4-channel A/D converter. The conversion time of the built-in A/D converter using the successive comparison method is 240 s. The necessary pin can be programmed to A/D analog input in 1-bit units. Up to the doubled voltage VDB (VDD x 2) can be input as the A/D input voltage.
VEE
10
VCPU
CPU power supply pin
VCPU
To A/D converter
P6-0/ADin1 (BRK9)
11~14
P6-3/ADin4 (BRK12)
I/O port 6 /AD analog input
~
VDD
Input instruction Release enables
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PIN No. Symbol Pin Name Function and Operation
22-bit CMOS I/O ports, allowing input and output to be programmed in 1-bit units. P10-0/COM1 15 ~ 18 I/O port 10 /LCD common output
Remarks
P10-3/COM4
P12-0/S1
~ ~
It can be set as LCD driver output through programming. Through a matrix with pins COM1 to COM4 and S1 to S18, a maximum of 72 segments can be displayed.
LCD potential VDD
19 ~ 22
P12-3/S4
I/O port 12 /LCD segment output
When the LCD OFF bit is set to "0", all of 8 pins of P10-0 to P12-3 become the LCD output of COM1 to COM4 and S1 to S4. Other LCD driver pins (S5 to S18) can be set to the LCD driver output for every pin.
VDD
P13-0/S6 23 ~ 26 I/O port 13 /LCD segment output Either of two drive systems can be selected: 1/4 duty1/2 bias system (frame frequency: 62.5 kHz) or 1/4 duty 1/3 bias system (frame frequency: 125 kHz). When 1/2 bias system is set, common output is VLCD, 1/2 VLCD and GND, and segment output is VLCD and GND. When 1/3 bias system is set, common output and segment output are VLCD, 1/3 VLCD, 2/3 VLCD and GND. If "1" is set to DISP OFF bit, common output is non-selected waveform and LCD display are all switched off. Pins P16-2 and P16-3 can be set to the high-speed oscillation pins Xin2 and Xout2 through programming. A 300-600 kHz ceramic or crystal oscillator is connected to Xin2 and Xout2 pins. This oscillation clock can be changed to CPU operation clock for high-speed CPU operation. During execution of the clock stop instruction, oscillation stops. Note: When changing the CPU clock to a high-speed oscillator clock, do so 100 ms or more after the high-speed oscillator is enabled.
P13-3/S8
P14-0/S9
~ ~
Input instruction
27 ~ 30
P14-3/S12
I/O port 14 /LCD segment output
Xout2
Rout2 RfXT2 VDD
31 ~ 32
P15-0/S13 / P15-1/S14
I/O port 15 /LCD segment output
Xin2
P16-0/S15 /Xin2
33 ~ 36
P16-3/S18 /Xout2
I/O port 16 /LCD segment output /High speed oscillator
(Xin2, Xout2)
~
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PIN No. Symbol Pin Name Function and Operation
4-bit CMOS I/O Port, allowing input and output to be programmed in 1-bit units. When the I/O port is set as input, the pull-up/pull-down state can be programmed in 1-bit units. If set as the input state of an I/O port and a backup release enable state, the backup state can be released by changing input state in the clock stop and the wait modes. Pins P3-0 to P3-2 are used as input/output pins of a serial interface circuit. The serial interface circuit corresponds to 2-wired, 3-wired and UART types. Serial clock edge, serial clock input/output and clock frequency are selectable, facilitating the control of various LSIs and communication between controllers. When interruption of a serial interface circuit is permitted, interruption occurs and a program is jumped to the 3rd address after the serial interface operation is completed. The P3-3 pin is used as 8-bit pulse counter input PCTRin. Since it is possible to select either or both of the rising edge and falling edge of the input pin, as well as count-up or count-down, the pin can be used as an input to a tape count.
Remarks
VDD RIN1
37
P3-0/SCK1 /RX1 (BRK1) P3-1/SDIO1 /TX1 (BRK2) P3-2/SI1 (BRK3) P3-3/PCTin (BRK4)
I/O port 3 /Serial clock input/ output 1/UART input 1 /Serial data input/ output 1/UART output 1
VDD
38
39
/Serial data input 1
40
/Pulse counter input
VDD
Input instruction Release enables
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PIN No. Symbol Pin Name Function and Operation Remarks
VDD
8-bit CMOS I/O Port, allowing input and output to be programmed in 1-bit units. 41 P4-0/INTR1 (BRK5) P4-1/INTR2 I/O port 4 /External interrupt input 1 /External interrupt input 2 /PLL inhibit input When P4-0 to P4-3 ports are set as the input and backup release enable states, the backup state in the clock stop and wait modes can be released by changing input state.
42
INH (BRK6)
VDD
43
P4-2/BUZR (BRK7)
/Buzzer output Pins P4-0 and P4-1 are also used as external interrupt input INTR1 and INTR2. When external interrupt is enabled and a 3-clock pulse of CPU (40 s: using 75 kHz oscillator) or longer is input to the INTR1 or INTR2 pin, an interrupt is generated and a program jumps to the 1st or 2nd address.
Input instruction Release enables (P4-0 to P4-2)
Electronic volume signal VDD
44
P4-3/VRout1 (BRK8)
I/O port 4 /Electronic volume output1
For input interrupt, input logic or rising/falling edge can be selected for each pin. The signal input from the INTR1 pin can measure the pulse width using the 8-bit internal timer. The signal can be used to detect a remote control signal.
VDD
The P4-1 pin is used as the PLL inhibit input INH . If the INH pin is set to the PLL inhibit enable state, the PLL is stopped during "L" level of the INH pin.
Input instruction Release enables (P4-3)
45
P5-0/VRin1
I/O port 5 /Electronic volume input1 /Electronic volume reference voltage input
The P4-2 pin is used as the buzzer output. For the buzzer output it is possible to select 4 frequencies, 1/1.56/2.08/3 kHz, with 4 modes: continuous output, single-shot output, 10-Hz intermittent output, and 10-Hz intermittent 1-Hz interval output.
Electronic volume signal VDD
46
P5-1/VRcom
47
P5-2/VRin2
/Electronic volume input 2
48
P5-3/VRout2
/Electronic volume output 2
Pins P4-3 and P5-0 to P5-3 are used as input/output pins for electronic volume. There are two electronic volume channels. An I/O port or electronic volume is selectable for every channel. Attenuation can be controlled from 0 dB to -78 dB and dB in 32 steps.
VDD
Input instruction (P5-0 to P5-3)
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PIN No. Symbol Pin Name Function and Operation
IF signal input pin. The input frequency is between 0.03 and 12 MHz. A built-in input amp and C coupling allow small-amplitude operation. The IF counter can store 20-bit data in memory. In Manual mode, gate On/Off control can be performed using an instruction. 49 IFin/IN IF signal input /Input port The input pin is used as an input port (IN port). In this case, the pin is for CMOS input, so that input clocks can be counted using the IF counter. Note: When a pin is set to IF input, the input is at high impedance in PLL-off mode. Note: Since the VPLL power supply is used in this circuit, an input state cannot be read when the VPLL power supply is in the OFF state.
Remarks
Rfin2 VPLL
VPLL
Input instruction
Pin to which power is applied for the PLL prescaler. 50 VPLL PLL Power supply pin Normally, the supply voltage to be applied is from 0.9 to 1.8 V. Current dissipation becomes low in PLL-off mode. 52 GND (PLL) Usually, the pin is connected to the VDD
VPLL
Programmable counter input pin. It is possible to select the pulse-swallow type (HF mode) or the direct divide type (LF mode) through programming. Local oscillation signal input The local oscillation output of 1 to 30 MHz is input in the HF mode; 0.5 to 4 MHz in the LF mode. A built-in input amp and C coupling allow small-amplitude operation. Note: The input is at high impedance in PLL-off mode.
Rfin1 VPLL
51
OSCin
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PIN No. Symbol Pin Name Function and Operation Remarks
PLL phase comparator output pins. Tristate output: When the program counter divider output is higher than the reference frequency, High level is output; when the output is lower, Low level; and when they match, high impedance. The doubler voltage VDB is used for phase comparator power supply. The VDB power supply potential is output for High level. The DO1 and DO2 pins incorporate 3 types of output resistance (5 k, 50 k, 100 k), which can be changed for each pin. 53 54 DO1/OT1/P DO2/OT2/N /Tin Phase comparator output /output port /P output /Tr. Input for LPF The DO2 pin can change output resistance automatically according to the phase difference of the PLL. Therefore, lock-up time is improved. The DO2 pin can be programmed to high-impedance or as an output port (OT1, OT2). The phase comparator charge pump control signal (P/N), which is used to configure an external charge pump, can be output from the DO1/2 pin. If the phase comparator charge pump control signal (P/N) is set, when the program counter divider output is higher than the reference frequency, P/N is output at H/L level; when the output is lower, L/H level; and when they match, L/L level.
VDB
Rout1
(DO1/OT1/P, DO2/OT2)
Tin Tout
VDB
Rout1~4
(Tin, Tout) Note: Tin/Tout setting
VDD
Input instruction (P9-0)
VDD
Pins P9-1 to P9-2 is 2-bit CMOS I/O ports. The P9-0 pin is a 1-bit N-ch open-drain I/O, allowing input and output to be programmed in 1-bit units. The P9-1 pin is used as the MUTE output. The MUTE output is usually used for muting control signal output. The MUTE bit can be set to "1" through change in the input of the I/O port input release (BRK) pin. The MUTE output logic can be set through programming. During system reset ( RESET = "L"), the P9-2 pin is pulled down and becomes the test mode input. Therefore, the pin is normally used at Low level or in open state during the reset condition. Through programming, it is possible to use the N-ch FET transistor for low path filter amplifiers (5.5 V voltage). As for FET transistors, Tin pin is set as gate input and Tout pin is set as drain output.
VDD
55
P9-0/Tout
I/O port 9 /Tr. Output for LPF
Input instruction (MUTE/P9-1)
56 57
MUTE/P9-1 P9-2/DDCK2 /TEST
/Mute output /Clock output 2 for doubler /TEST mode input
VDD
VDD
Rin2
Input instruction, Reset (P9-2/DDCK2/TEST)
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PIN No. Symbol Pin Name Function and Operation
The port 8 is a 4-bit N-ch open-drain I/O port, allowing control of ON/OFF for an output transistor to be programmed in 1-bit units When an output is set as OFF, the pin can be used as an input port. When the backup release enable state is set, the backup state in the clock stop and wait modes can be released by a change in the input or output pin. The I/O port is N-ch open-drain I/O. Up to 5.5 V can be input to or output from the I/O port. This pin is used to configure the switching regulator for VT. The voltage is doubled by the doubler clock output DDCK1 (P8-1) or DDCK2 (P9-2). The divided voltage is input to the detected doubler voltage VDET pin (P8-0) to control the doubler clock. The DDCK1 output is 5.5V N-ch output. The VT doubled voltage is doubled to 5 V through the use of an external transistor. The DDCK2 output is CMOS output The voltage can be doubled through the use of an external transistor. For the doubler clock, it is possible to select from three types of dividing frequency: crystal oscillator, high-speed oscillator and OSCin input. It is also possible to select through programming the comparator reference potential of the VDET input: either 0.75 V or 1.0 V. Pins P8-1 to P8-3 are used as serial interface circuit (SIO) input/output pins. The serial interface circuit corresponds to 2-wired type, 3-wired type, and UART. Serial clock edge, serial clock input/output, and clock frequency can be selected, facilitating the control of various LSIs and communication between controllers. When interrupts of a serial interface circuit are enabled, an interrupt is generated after serial interface and the program jumps to the 3rd address. Input pin for system reset signals. The input uses built-in Schmitt circuit.
Remarks
Detected doubler voltage input
VDD
P8-0/VDET (BRK13)
I/O port 8 /Detected doubler voltage input /Serial data input 2 /Doubler clock output 1
Input instruction Release enables (P8-0)
P8-1/SI2 /DDCK1 (BRK14) 58 ~ 61 P8-2/SCK2 /RX2 (BRK15) P8-3/SDIO2 /TX2 (BRK16)
/Serial clock input/ output 2 /UART input 2 /Serial clock input/ output 2 /UART output 2
VDD
Input instruction Release enables (P8-1, P8-3)
62
RESET
Reset input
RESET takes place while at Low level; at High level, the program starts from address "0" after 100 ms standby.
Normally, if voltage is applied to the VCPU pin, the system is reset (power-on reset).Therefore, this pin should be set to High level during operation.
VCPU
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Description of Operations
CPU
The CPU consists of a program counter, a stack register, an ALU, program memory, data memory, a G-register, a data register, a DAL address register, a carry flip-flop (F/F), a judge circuit, interrupt stack register and an interrupt circuit.
1.
Program Counter (PC)
The program counter is a 14-bit binary up-counter used to address program memory (ROM). The program counter is cleared by a system reset and starts from address 0. The PC is normally incremented by 1 at the execution of each instruction. However, executing a Jump or Call instruction loads the address specified in the operand of the instruction to the PC. When an instruction with a skip function (the AIS, SLTI, TMT, RNS instructions, etc.) is executed and the result of the instruction satisfies the skip condition, the PC is incremented by 2 and the next instruction is skipped. When an interrupt is received, the system loads the vector address corresponding to the interrupt. Note: The program memory (ROM) uses the address range 0000H to 1FFFH. Access to addresses outside this range is prohibited.
Contents of program counter (PC) Instruction PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
JUMP ADDR1
0
Instruction operand (ADDR1)
CALL ADDR2 DAL ADDR3, (r) (DAL bit = 0) DAL (DA) (DAL bit = 1) RN, RNS, RNI
0
Instruction operand (ADDR2) Contents of general register (r)
0
0
0
0
Instruction operand (ADDR3)
DAL address register (AR)
Contents of stack register
When interrupt received Power-on reset, reset by RESET pin 0 0 0 0 0
Vector addresses for interrupt 0 0 0 0 0 0 0 0 0
Interrupt source INTR1 pin INTR2 pin / Timer port Serial interface / timer port / decreased voltage detection Timer counter
Vector address 0001H 0002H 0003H 0004H
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2. Address Stack Register (ASR)
The address stack register consists of 16 x 14 bits. When the subroutine call instruction is executed or an interrupt is processed, this register stores a value equal to the contents of the program counter + 1 (that is, the return address). Executing the return instruction (RN, RNS, RNI) loads the contents of the address stack register to the program counter. There are 16 stack levels available and nesting occurs for up to 16 levels. The address stack register is mapped to I/O and can be read/written by the input and output instructions.
3. ALU
The arithmetic and logic unit (ALU) has binary 4-bit parallel addition/subtraction functions, logical operation, comparison and multiple bit judge functions. The CPU does not include an accumulator; all operations use the contents of the data memory directly.
4. Program Memory (ROM)
The program memory consists of 16 bits x 8192 steps and is used for storing programs. The usable address range consists of 8192 steps between addresses 0000H and 1FFFH. The program memory divides the 8192 into eight separate steps and consists of pages 0 to 7. The JUMP and CALL instructions can be freely used throughout all 8192 steps. When the data refer DAL (DAL instruction) is executed, the program memory addresses 0000H to 03FFH (page 0) are used as data areas; when the indirect refer DAL instruction (DALR instruction) is executed, the program memory addresses 0000H to 0FFFFH (pages 0 to 3) are used as data areas. Execution of these instructions enables their 16-bit contents to be loaded into the data register. Note: Set the data area in program memory to addresses outside the program loop. Note: The program counter used to set the program memory has 14 bits and can specify a program memory up to address 3FFF. Do not specify non-existing addresses from 2000H to 3FFFH.
ROM 16 bits 0000H Area available to DAL instruction Vector addresses at interrupt 0000H Jump destination address at initialization Interrupt vector address 0001H 0002H 0003H 0004H INTR1 pin INTR2 pin / timer port Serial interface / timer port / decreased voltage detection Timer counter
Page 0 (1-k steps)
Area available to JUMP instruction
0400H Page 1 0800H Page 2 0C00H Page 3 1000H Page 4 1400H Page 5 1800H Page 6 1C00H Page 7 1FFFH
Area available to DALR instruction
Area available to CALL instruction
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5. Data Memory (RAM)
The data memory consisting of 4 bits x 512 words is used to store data. These 512 words are expressed in a row address (4 bits) and column address (4 bits). 348 words (row address = 04H to 1FH) within the data memory are addressed indirectly by the G-register. Therefore it is necessary to specify the row address with the G-register before the data in this area can be processed. The addresses 00H to 0FH within the data memory are known as general registers, and can be used simply by specifying the relevant column address (4 bit). These sixteen general registers can be used for operations and transfers with the data memory, and may also be used as normal data memories. Note: The column address (4 bits) that specifies the general register is the register number of the general register. Note: All row addresses (00H to 1FH) can be specified indirectly with the G-register. Note: The LD and ST instructions can directly address 256 words of data memory (row address area 00H to 0FH).
COLUMN ADDRESS: DC 0123456789ABCDEF ROW ADDRESS: DR * 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 Row address area 00H to 1FH can be indirectly specified. 1D 1E 1F General register (any register within 000H to 00FH)
Row addresses (04H to 2FH) indirectly specified by G-register
The LD and ST instructions can directly specify row addresses (00H to 0FH).
*
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6. G-register (G-REG)
The G-register is a 5-bit register used for addressing the row address (DR = 00H to 1FH) of the data memory's 512 words. This register is located on the I/O map and accessed by input-and-output instruction. The 5-bit contents can be directly set by execution of the STIG instruction. (Refer to Register Ports.) The contents of this register are effective when the MVGD or MVGS instruction is executed, and are not affected through execution of any other instructions. The contents of the G-register are evacuated to the interrupt stack register when an interrupt request is generated, and returned to the G-register during execution of the RNI instruction. (Refer to Interrupt Stack Register.)
7. Data Register (DATA REG)
The data register consists of 16 bits and loads 16 bits of data from any address in the program memory on execution of the DAL instruction. This register is used as one of the ports. The contents of the register are loaded into the data memory in 4-bit units when the IN1 instruction among the I/O instructions is executed. (Refer to Register Ports.) The contents of data register are evacuated to the interrupt stack register when an interrupt request is generated, and returned to the data register during execution of the RNI instruction. (Refer to Interrupt Stack Register.)
8. DAL Address Register (AR)
The DAL address register consists of 14 bits. When the DALR instruction is executed, 16 bits of the data of the program memory on the address specified by the DAL address register is loaded to the data register. The contents in the DAL address register are automatically increased by one whenever the DALR instruction is executed. The contents of the data register can be transferred to the DAL address register by execution of the MVAR instruction. The DAL address register is located on the I/O map and accessed by input and output instructions. (Refer to Register Ports.)
9. Carry Flag (Ca Flag)
The carry flag register is set when either Carry or Borrow is issued in the result of calculation instruction execution, and is reset if neither of these is issued. The flag is located on the I/O map and can be accessed by the input and output instructions. (Refer to Register Port.) The contents of a carry flag are changed by execution of only the addition, subtraction, CLT, CLTC, SHRC or RORC instruction and are not affected by execution of other instructions. The contents of carry flag are evacuated to the interrupt stack register when an interrupt request is generated, and returned to the carry flag during execution of the RNI instruction. (Refer to Stack Register.)
10.
Interrupt Stack Register (ISR)
This register consists of 4 levels and 26 bits. When an interrupt occurs, the contents of the G-register (5 bits), data select (4 bits), carry flag (1 bit) and data register (16 bits) are automatically evacuated to the interrupt stack register. After interrupt processing has been completed, these contents are returned to each register by the RIN instruction. Four levels of stack and nesting are allowed in the interrupt stack register. (Refer to Interrupt Stack Register.)
11.
Judge Circuit (J)
This circuit judges the skip conditions when an instruction with the skip function is executed. The program counter is increased by two when the skip conditions are satisfied, and the subsequent instruction is skipped. There are 15 instructions with a wide variety of skip functions available. (Refer to the items marked with a "*" symbol in Instruction Function and Operation Table.)
12.
Interrupt Circuit
An interrupt circuit branches to the various vector addresses according to the demands from peripheral hardware and performs different types of interrupt processing. (Refer to Interrupt Function.)
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13. Instruction Set Table
A total of 59 instruction sets are available, and all of these are single-word instructions. These instructions are expressed with a 6-bit instruction code.
Upper 2 bits Lower 4 bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 0 1 2 3 4 5 6 7 8 9 A B C D E AI AIC SI SIB ORIM ANIM XORIM MVIM AD AC SU SB ORR ANDR XORR 00 0 M, I M, I M, I M, I M, I M, I M, I M, I r, M r, M r, M r, M r, M r, M r, M CLT CLTC MVGD r, M r, M r, M ST M*, r LD r, M* TMTR TMFR SEQ SNE 01 1 r, M r, M r, M r, M JUMP ADDR1 10 2 SLTI SGEI SEQI SNEI TMTN TMT TMFN TMF IN1 IN2 IN3 OUT1 OUT2 OUT3 DAL SHRC RORC CAL ADDR2 STIG SKP, SKPN RN, RNS 1111 F MVSR M1, M2 MVGS M, r WAIT CKSTP XCH DI, EI, RNI DALR MVAR NOOP M P 11 3 M, I M, I M, I M, I M, N M, N M, N M, N M, C M, C M, C M, C M, C M, C ADDR3, r M M I*
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14. Instruction Function and Operation Table (Description of the symbols used in the table)
M M* Data memory address Normally, an address within 000H to 03FH in the data memory. Data memory address (256 words) An address within 000H to 0FFH in the data memory. (Effective only during execution of the ST or LD instruction) General register An address within 000H to 00FH in the data memory. Program counter (14 bits) Address stack pointer (14 bits) Address stack register (14 bits) Interrupt stack pointer (2 bits) Interrupt stack register (26 bits) G-register (5 bits) Data register (16 bits) Immediate data (4 bits) Immediate data (6 bits, effective only during execution of the STIG instruction) Bit position (4 bits) All "0" Port code number (4 bits) Port code number (4 bits) General register number (4 bits) Program memory address (13 bits) Upper 6 bits of program memory address within page 0 DAL address register (14 bit) Carry Carry flag Wait condition Borrow Ports used during execution of the IN1 to IN3 instructions Ports used during execution of the OUT1 to OUT3 instructions Contents of registers or data memory Contents of the port indicated by the code number C (4 bits) Contents of data memory indicated by the register or data memory Contents of program memory (16 bits) Instruction code (6 bits) Command with skip function Data memory column address (4 bits) Data memory row address (2 bits) Data memory row address (4 bits, effective only during execution of the ST or LD instruction) Bit data of data memory contents (1 bit)
r PC ASP ASR ISP ISR G DATA I I* N - C CN RN ADDR1 ADDR2 AR Ca CY P b IN1~IN3 OUT1 ~ OUT3 () []C [] []P IC * DC DR DR* (M) b0 ~ (M) b3
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Instruction Set
Mnemonic
Skip Function
Machine Language (16 Bits) Function Operation IC (6 Bits) 000000 A (2 Bits) DR B (4 Bits) DC C (4 Bits) I
AI Addition instruction
M, I
Add immediate data M (M) + I to memory Add immediate data to memory with M (M) + I + ca carry Add memory to general register r (r) + (M)
AIC
M, I
000001
DR
DC
I
AD
r, M
001000
DR
DC
RN
AC
r, M
Add memory to general register with r (r) + (M) + ca carry Subtract immediate data from memory Subtract immediate data from memory with borrow Subtract memory from general register Subtract memory from general register with borrow * M (M) - I M (M) - I - b
001001
DR
DC
RN
SI Subtraction instruction
M, I
000010
DR
DC
I
SIB
M, I
000011
DR
DC
I
SU
r, M
r (r) - (M)
001010
DR
DC
RN
SB
r, M
r (r) - (M) - b
001011
DR
DC
RN
SLTI
M, I
Skip if memory is less than immediate Skip if (M) < I data Skip if memory is greater than or equal to immediate data Skip if memory is equal to immediate data Skip if memory is not equal to immediate data Skip if general register is equal to memory Skip if general register is not equal to memory Set carry flag if general register is less than memory, or reset if not Set carry flag if general register is less than memory with carry or reset if not Skip if (M) > I =
110000
DR
DC
I
SGEI
M, I
*
110001
DR
DC
I
SEQI Compare instruction
M, I
*
Skip if (M) = I
110010
DR
DC
I
SNEI
M, I
*
Skip if (M) I
110011
DR
DC
I
SEQ
r, M
*
Skip if (r) = (M)
010010
DR
DC
RN
SNE
r, M
*
Skip if (r) (M) (CY) 1 if (r) < (M) or (CY) 0 if (r) > (M) = (CY) 1 if (r) < (M) + (ca) or (CY) 0 if (r) > (M) + = (Ca)
010011
DR
DC
RN
CLT
r, M
011100
DR
DC
RN
CLTC
r, M
011101
DR
DC
RN
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Instruction Set
Mnemonic
Skip Function
Machine Language (16 Bits) Function Operation IC (6 Bits) 0101 0110 A (2 Bits) DR* (4 bits) DR* (4 bits) DR B (4 Bits) DC DC C (4 Bits) RN RN
LD ST
r, M* M*, r
Load memory to general register Store memory to general register Move memory to memory in same row Move immediate data to memory Move memory to destination memory referring to G-register and general register
r (M*) M* (r) (DR, DC1) (DR, DC2) MI
MVSR M1, M2
001111
DC1
DC2
MVIM Transfer instruction
M, I
000111
DR
DC
I
MVGD r, M
[(G), (r)] (M)
011110
DR
DC
RN
MVGS M, r
Move source memory referring to G-register and (M) [(G), (r)] general register to memory Move immediate data to G-register G I*
011111
DR
DC
RN
STIG
I*
111111 DR
I* DC
0010
MVAR
Move DATA register data to DAL AR (DATA) address register M, C Input IN1 port data to memory Output contents of memory to OUT1 port Input IN2 port data to memory Output contents of memory to OUT2 port Input IN3 port data to memory Output contents of memory to OUT3 port M [IN1] C [OUT1] C (M) M [IN2] C [OUT2] C (M) M [IN3] C [OUT3] C (M)
111111
1001
IN1
111000
CN
OUT1 I/O instruction
M, C
111011
DR
DC
CN
IN2
M, C
111001
DR
DC
CN
OUT2
M, C
111100
DR
DC
CN
IN3
M, C
111010
DR
DC
CN
OUT3
M, C
111101
DR
DC
CN
ORR
r, M
Logical OR of general register and r (r) (M) memory Logical AND of general register and r (r) (M) memory Logical OR of memory and immediate data Logical AND of memory and immediate data Logical exclusive OR of memory and immediate data Logical exclusive OR of general register and memory M (M) I
001100
DR
DC
RN
Logical Operation instruction
ANDR
r, M
001101
DR
DC
RN
ORIM
M, I
000100
DR
DC
I
ANIM
M, I
M (M) I
000101
DR
DC
I
XORIM M, I
M (M) I
000110
DR
DC
I
XORR r, M
r (r) (M)
001110
DR
DC
RN
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Instruction Set
Mnemonic
Skip Function
Machine Language (16 Bits) Function Operation IC (6 Bits) A (2 Bits) B (4 Bits) C (4 Bits)
TMTR
r, M
*
Test general register bits by memory bits, then skip if all bits specified are true Test general register bits by memory bits, then skip if all bits specified are false Test memory bits, then skip if all bits specified are true Test memory bits, then not skip if all bits specified are false Test memory bits, then skip if all bits specified are true Test memory bits, then not skip if all bits specified are false Skip if carry flag is true Skip if carry flag is false Call subroutine Return to main routine
Skip if r [N (M)] = all "1"
010000
DR
DC
RN
TMFR
r, M
*
Skip if r [N (M)] = all "0"
010001
DR
DC
RN
Bit judge instruction
TMT
M, N
*
Skip if M (N) = all "1"
110101
DR
DC
N
TMF
M, N
*
Skip if M (N) = all "0"
110111
DR
DC
N
TMTN
M, N
*
Skip if M (N) = not all "1" Skip if M (N) = not all "0" Skip if (CY) = 1 Skip if (CY) = 0 ASR (PC) 1 and PC ADDR2 ASP (ASP) + 1 PC (ASR) ASP (ASR) - 1 PC (ASR) and skip ASP (ASR) - 1
110100
DR
DC
N
TMFN
M, N
*
110110
DR
DC
N
SKP SKPN Subroutine instruction
* *
111111 111111
00 01

0011 0011
CALL ADDR2
101
ADDR2 (13 bits)
RN
111111
10
0011
RNS
*
Return to main routine and skip unconditionally
111111
11
0011
Jump instruction
JUMP ADDR1
Jump to address specified
PC ADDR1
10
ADDR1 (13 bits)
DI Interrupt instruction EI
Reset IMF Set IMF
(Note) IMF 0 (Note) IMF 1
111111 111111
00 01

0111 0111
RNI
PC (ASR) PC (ASR) - 1 Return to main Ca, G, DATA, DATA routine and set IMF SELECT (ISR) (Note) ISP (ISP) - 1 IMF 1
111111
11
0111
Note: The IMF bit is an interrupt master enable flag located on the I/O map. (Refer to Interrupt Functions.)
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Instruction Set
Mnemonic
Skip Function
Machine Language (16 Bits) Function Operation IC (6 Bits) 111111 A (2 Bits) DR B (4 Bits) DC C (4 Bits) 0000
SHRC M
Shift memory bits to 0 (M) b3 (M) b2 right direction with (M) b1 (M) b0 (CY) carry Rotate memory bits to right direction with carry Exchange memory bits mutually (M) b3 (M) b2 (M) b1 (M) b0 (CY) (M) b3 (M) b0, (M) b2 (M) b1
RORC M
111111
DR
DC
0001
XCH
M
111111
DR
DC
0110
DAL ADDR3, r
Load program in DATA [ADDR3 + page 0 to DATA (r)] P in page 0 register (Note) Load program memory to DATA register referring to DAL address register, and increment DAL address register At P = "0" H, the condition is CPU waiting (soft wait mode)
111110
ADDR3 (6 bits)
RN
Other instructions
DALR
DATA [(AR)]P AR (AR) + 1
111111
1000
WAIT
P
At P = "1" H, all functions except for clock generator enter the waiting state (hard wait mode) Clock generator stop No operation
Wait at condition P
111111
P
0100
CKSTP
Stop clock generator to MODE condition
111111

0101
NOOP
111111
1111
Note: The lower 4 bits of the 10 bits of program memory specified by the DAL instruction (DAL ADDR2, r) are addressed indirectly by the contents of the general register. The 13 bits of program memory specified by DALR instruction are used for indirect addressing. Note: The DAL address register (AR) is located on the I/O map. (Refer to Register Ports.) Note: The DAL or DALR instruction run-time is two machine cycles.
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I/O Map, Data Select Port (L/K1A)
All the ports within the device are expressed with a matrix of six I/O instructions (OUT1 to 3 instructions and IN1 to 3 instructions) and 4-bit code numbers. The allocation of these ports is shown on the following page in the form of an I/O map. The ports used in the execution of the various I/O instructions on the horizontal axis of the I/O map are allocated to the port code numbers indicated on the vertical axis. The G-register, data register and DAL bits are also used as ports. The OUT1 to 3 instructions are specified as output ports, and the IN 1 to 3 instructions are specified as input ports. Note: The ports indicated by the angled lines on the I/O map do not actually exist within the device. When data is output to a non-existing output port by execution of the output instruction, the contents of other ports and data memories are not affected. When a non-existing input port is specified by execution of an input instruction, the data loaded from the data memory assumes "don't care" status. Note: The output ports marked with an asterisk (*) on the I/O map are not used. Data output to these ports assumes "don't care" status. Note: The Y1 contents of the ports expressed in 4 bits correspond to the LSB and the Y8 contents correspond to the MSB in the data memory. The ports specified with the six I/O instructions and code number C are coded in the following manner.
[K/L] m n (o) (Pp) Pages (1 to 3) Contents of selected port (indirectly specified data, 0 to F (HEX)) I/O instruction operand CN (0 to F (HEX)) The six I/O instructions are coded with digits 1 to 3
I/O instruction m
OUT1 1
OUT2 2
OUT3 3
IN1 1
IN2 2
IN3 3
Indicates input/output ports. K: Input port (instructions IN1 to 3) L: Output port (instructions OUT1 to 3)
Example:
The setting for the G-register is allocated to code 8 and 9 in the OUT1 instruction. The encoded expression at this time becomes L18 and L19.
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Data port (L10 to 16, K10 to 11) on the I/O map is divided into 16 and indirectly specified by the contents of the data select port (L/K1A). The indirectly specified port is accessed by the OUT1 instruction with the operand [CN = 0 to 6H] or IN1 instruction with the operand [CN = 0 to 1H]. Whenever the data select port accesses the data port, it is automatically incremented by 1. The data select port has a 4-bit interrupt stack register. When an interrupt request is generated, the 4 bits in the data select port are evacuated to the interrupt stack register specified by the interrupt stack pointer, and returned to the data select port during execution of the RNI instruction.
L/K10(6)
Y1
ISP0
Y2
ISP1
Y4
*/0
Y8
*/0
Interrupt stack pointer
L/K10(A) 0
ISRS0 ISRS2 ISRS4 ISRS8
1 2 3
Interrupt stack register Interrupt processing Execution of the RIN instruction
L10 L15, K10 K11
Y1 Y2
SEL2
Y4
SEL4
Y8
SEL8
Y1 (0) (1) (2)
Y2
Y4
Y8
L/K1A
SEL1
Data select
(F)
< Indirect specification by the data selection port >
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I/O Map (IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C))
L1 Page 1 Y1 0 Y2 OUT1 Y4 Y8 Y1 Y2 L2 OUT2 Y4 Y8 Y1 Y2 L3 OUT3 Y4 Y8 Y1 Y2 K1 IN1 Y4 Data port 1 EF4 (TIMER) Data port 2 ILR4 (TIMER) I/O port 3 output data -0 -1 -2 -3 F0 F1 IF data 2 -3 F4 F5 IF data 3 -3 F8 F9 IF data 4 -3 F12 F13 IF data 5 CK1 LPFON -0 MUTE control POL Break MUTE ENA G0 I/O port 8 output data -1 -2 -3 Busy F16 F17 F18 F19 F14 F15 STOP F/F BUZER 10 Hz VDO OFF F/F 0 I/O port 8 input data Unknown -0 -1 I/O port 9 input data 0 -0 -1 -2 -2 -3 IN -0 F10 F11 AD4 F6 F7 AD0 IF data 1 F2 F3 IMF ILR1 (INTR1) EF1 (INTR1) Y8 Y1 Y2 K2 IN2 Y4 Y8 Y1 Y2 K3 IN3 Y4 Y8
Data port 1 EF1 (INTR1) Data port 2 ILR1 (INTR1) Data port 3
Interrupt enable flag EF2 EF3 (INTR2/TM) (SIO/TP/W) Interrupt latch reset ILR2 (INTR2/TM) ILR3 (SIOTP/W)
Interrupt enable flag EF2 (INTR2/TM) ILR2 (INTR2/TM) EF3 (SIO) ILR3 (SIOTP/W) EF4 (TIMER) ILR4 (TIMER) I/O port 3 input data 0 -0 -1 -2 -3
1
Interrupt latch
2
INTR1 control POS1 NEG1
INTR2 control POS2 NEG2
Interrupt master flag 0 0
3
Data port 4 AS SEL0 Data port 5
A/D converter control AS SEL1 AS SEL2 STA -0
I/O port 4 output data -1 -2
A/D converter data AD1 AD2 AD3 -0
I/O port 4 input data -1 -2 -3
DO1 control R0 R1 M0 M1 -0
I/O port 5 output data -1 -2
A/D converter data AD5 Busy 0 -0
I/O port 5 input data -1 -2 -3
4
5
Data port 6 R0
DO2 control 1 R1 M0 M1 -0
I/O port 6 output data -1 -2
I/O port 6 input data -1 -2 -3
6
Data port 7 AUTO1
DO2 control 2 ENA PN CK0 POL
7 DISP OFF 8 G0 9 G4 A S1 B CA flag
LCD driver control LCD OFF BIAS *
UNLOCK RESET
IF monitor MANUAL OVER 0 UNLOCK MUTE G3
Unlock detect ENA Unknown MUTE control IO1 POL
G-register 1 G1 G2 G3
MUTE
G-register 1 G1 G2
G-register 2 * Data select S2 * S4 * S8 * POS NEG DOWN * -0 -1 -2 -3 Pulse counter control 2 d3 CTR RESET OVER RESET * * -0 I/O port 5 control -1 -2 -3 d0 * * Timer reset 2 Hz F/F Clock Timer port interrupt control CK SEL ENA -0 I/O port 3 control -1 -2 -3 SEL1 CA flag G4 0
G-register 2 0 Data select SEL2 0 SEL4 0 SEL8 0 PC0 Data-register 1 (DATA) d1 d2 d3 PC4 2 Hz F/F 10 Hz 0 Timer 100 Hz 200 Hz -0
I/O port 10 input data -1 -2 -3
Pulse counter control 1
I/O port 4 control
Pulse counter data PC1 PC2 PC3 -0
I/O port 12 input data -1 -2 -3
C d0 D d4 E d8 F d12
Data-register 1 (DATA) d1 d2
Pulse counter data PC5 PC6 PC7 -0
I/O port 13 input data -1 -2 -3
Data-register 2 (DATA) d5 d6 d7 CK
Timer counter control PW CR Disable CR -0
I/O port 16 control -1 -2 -3 d4
Data-register 2 (DATA) d5 d6 d7 OVER
Pulse counter data 0 0 0 -0
I/O port 14 input data -1 -2 0 -3 0
Data-register 3 (DATA) d9 d10 d11 ID0
Timer counter interrupt detect data 1 ID1 ID2 ID3 I/O port 16 data ID7 -0 -1 -2 -3 d12 d8
Data-register 3 (DATA) d9 d10 d11 CT0
Timer counter data 1 CT1 CT2 CT3
I/O port 15 input data -0 -1
Data-register 4 (DATA) d13 d14 d15 ID4
Timer counter interrupt detect data 2 ID5 ID6
Data-register 4 (DATA) d13 d14 d15 CT4
Timer counter data 2 CT5 CT6 CT7 -0
I/O port 16 input data -1 -2 -3
Refer to the next page
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L/K1A Data select SEL1 SEL2 SEL4 SEL8 I/O L10 OUT1 K10 IN1 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 L11 OUT1 Y4 Y8 Y1 Y2 K11 IN1 Y4 Y8
L/K1A
0
Y1
Y2
Address stack pointer (ASP) ASP0 ASP1 ASP2 ASP3 ASP0
Address stack pointer (ASP) ASP1 ASP2 ASP3 AR0
DAL address 1 (AR) AR1 AR2 AR3 DA0
DAL address 1 (AR) DA1 DA2 DA3
1 ASS0 2 ASR0 3 ASR4 4 ASR8 5 ASR12 6 ISP0 7 ISS0 8 ISRG0 9 ISRG4 A ISRdS0 B ISRCA C ISRd0 D ISRd4 E ISRd8
Address stack select ASS1 ASS2 ASS3 STKS0
Address stack select STKS1 STKS2 STKS3 AR4
DAL address 2 (AR) AR5 AR6 AR7 DA4
DAL address 2 (AR) DA5 DA6 DA7
Address stack register 1 (ASR) ASR1 ASR2 ASR3 ASR0
Address stack register 1 (ASR) ASR1 ASR2 ASR3 AR8
DAL address 3 (AR) AR9 AR10 AR11 DA8
DAL address 3 (AR) DA9 DA10 DA11
Address stack register 2 (ASR) ASR5 ASR6 ASR7 ASR4
Address stack register 2 (ASR) ASR5 ASR6 ASR7 AR12
DAL address 4 (AR) AR13 TROM * DA12
DAL address 4 (AR) DA13 TROM 0
Address stack register 3 (ASR) ASR9 ASR10 ASR11 ASR8
Address stack register 3 (ASR) ASR9 ASR10 ASR11 SO0
Serial interface output data 1 SO1 SO2 SO3 SI0
Serial interface input data 1 SI1 SI2 SI3
Address stack register 4 (ASR) ASR13 * * ASR12
Address stack register 4 (ASR) ASR13 0 0 SO4
Serial interface output data 2 SO5 SO6 SO7 SI4
Serial interface input data 2 SI5 SI6 SI7
Interrupt stack pointer (ISP) ISP1 * * ISP0
Interrupt stack pointer (ISP) ISP1 0 0 SO8
Serial interface output data 3 SO9 SOE SOF SI8
Serial interface input data 3 SI9 SIE SIF
Interrupt stack select ISS1 * * ISS0
Interrupt stack select ISS1 0 0 M0
Serial interface control 1 M1 PORT SEL SIO BUSY1
Serial interface monitor 1 SOERR RX F/F BUSY2
Interrupt stack register (ISR) ISRG1 ISRG2 ISRG3 ISRG0
Interrupt stack register (ISR) ISRG1 ISRG2 ISRG3 CK0
Serial interface control 2 CK1 OSC0 OSC1 OCT0
Serial interface monitor 2 OCT1 OCT2 OCT3
Interrupt stack register (ISR) * * * ISRG4
Interrupt stack register (ISR) 0 0 0 MASTER
Serial interface control 3 POL N-chS SIS ICT0
Serial interface monitor 3 ICT1 ICT2 ICT3
Interrupt stack register (ISR) ISRdS1 ISRdS2 ISRdS3 ISRdS0
Interrupt stack register (ISR) ISRdS1 ISRdS2 ISRdS3 STPS
Serial interface control 4 SWENA MSB SOS
Interrupt stack register (ISR) * * * ISRCA
Interrupt stack register (ISR) 0 0 0 STA0
Serial interface control 5 STA1 STA2 STA3
Interrupt stack register (ISR) ISRd1 ISRd2 ISRd3 ISRd0
Interrupt stack register (ISR) ISRd1 ISRd2 ISRd3 STP0
Serial interface control 6 STP1 STP2 STP3 Decreased voltage detection voltage trimming register F/F RESET TR0 TR1 TR2 TR3
Interrupt stack register (ISR) ISRd5 ISRd6 ISRd7 ISRd4
Interrupt stack register (ISR) ISRd5 ISRd6 ISRd7 TSTA1
Serial interface control 7 TSTA2 STP
Interrupt stack register (ISR) ISRd9 ISRd10 ISRd11 ISRd8
Interrupt stack register (ISR) ISRd9 ISRd10 ISRd11
Decreased voltage detection control 1 WAIT ENA INH ENA VSTOP ENA * TT0
Constant-voltage trimming register TT1 TT2 TT3
Interrupt stack register (ISR) F ISRd12 ISRd13 ISRd14 ISRd15 ISRd12
Interrupt stack register (ISR) ISRd13 ISRd14 ISRd15
Decreased voltage detection control 2 STOP F/F RESET INT LB SEL TIM SEL BREAK ENA TA0
PLL amplifier trimming register TA1 TA2 TA3
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L/K1A Data select S1 S2 S4 S8 I/O L12 OUT1 L13 OUT1 Y4 Y8 Y1 Y2 Y4 Y8 Y1 Y2 S13 * COM1 COM2 S14 -3 COM1 COM2 S15 -3 COM1 COM2 S16 -3 S1 -3 COM1 COM2 S2 -3 COM1 COM2 S3 * COM1 COM2 S4 COM1 I/O port 9 control * 9 -0 A I/O port 12 control -0 C -0 -1 -2 -3 COM1 COM2 S9 -3 COM1 COM2 S10 -3 COM1 COM2 S11 * COM1 COM2 S12 F COM1 COM2 COM3 COM4 S15 S16 S17 S18 INV ON OSC2 ON CK SEL * TA0 TA1 TA2 TA3 COM3 COM4 S13 COM3 COM4 S9 COM3 COM4 S5 -1 -2 * COM1 COM2 S6 -3 COM1 COM2 S7 COM1 COM2 S8 COM3 COM4 PD30 COM3 COM4 PU30 COM3 COM4 BP3 COM2 S5 COM3 COM4 VC0 COM3 COM4 COM3 COM4 COM3 COM4 COM1 COM2 COM3 COM4 COM1 COM2 S18 COM3 COM4 VDET SEL COM1 COM2 S17 COM3 COM4 CH1 COM3 COM4 VR4 COM3 COM4 VR0 COM3 COM4 BM0 COM3 COM4 BF0 L14 OUT1 Y4 Y8 Y1 Y2 L15 OUT1 Y4 Y8 Y1 Y2 L16 OUT1 Y4 Y8
L/K1A
0
Y1
Y2
I/O port 9 output data -0 -1 -2
Buzzer output control 1 BF1 * BEN NC
IF counter control 1 IFin Prescaller IN 0
1 -0 2 -0 3 -0 4 -0
I/O port 10 output data -1 -2
Buzzer output control 2 BM1 BUZR ON POL
IF counter control 2
STA/ STP
MANUAL
G0
G1
I/O port 11 output data -1 -2
Electric volume data 1 VR1 VR2 VR3 #0
TEST port 1 #1 #2 #3
I/O port 12 output data -1 -2
Electric volume data 2 * * * #4 *
TEST port 2 * *
I/O port 13 output data -1 -2
Electric volume control CH2 VR MUTE -dB
I/O port 14 output data 5 -0 -1 -2
DC/DC converter control 1 0 VDET ENA *
6 -0 7
I/O port 15 output data -1 *
Interrupt priority 1 PRI1-0 PRI1-1
Interrupt priority 2 PRI2-0 PRI2-1 DD0
DC/DC converter control 2 DD1 DD2 DD3
Interrupt priority 3 PRI3-0 PRI3-1
Interrupt priority 4 PRI4-0 PRI4-1 DDCK1/2
DC/DC converter control 3 DDCK ENA POL *
8
Doubler voltage control for CPU VC1 CLAMP OSC2 HF 0 BP8
PLL mode select * 0 * 0 0 INH ENA
I/O port 10 control -1 -2
I/O port 2 brake permit BP4 BP6
I/O port 3 pull-up PU31 PU32 PU33 P0
Programmable counter 1 P1 P2 P3
B
I/O port 3 pull-down PD31 PD32 PD33 P4
Programmable counter 2 P5 P6 P7
I/O port 13 control -1 -2
I/O port 13 / Segment select S6 S7 S8 P8
Programmable counter 3 P9 P10 P11 Decreased voltage detection voltage trimming register P15 TR0 TR1 TR2 TR3
D -0 E -0
I/O port 14 control -1 -2
I/O port 14 / Segment select S10 S11 S12 P12
Programmable counter 4 P13 P14
I/O port 15 control -1 *
I/O port 15 / Segment select S14 * * R0
Reference select R1 R2 R3 TT0
Constant-voltage trimming register TT1 TT2 TT3
I/O port 16 / segment select
Clock generator control
PLL amplifier trimming register
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System Reset
The device system will be reset when the RESET pin is subject to the "L" level or when a voltage of 0 V 1.2 V to 3.6 V is supplied to the VCPU pin (power-on reset). On system reset, the program will start from "0" address immediately after a standby time of 100 ms following the startup of the low-speed oscillator. Since the power-on reset function is being used, the RESET terminal should be fixed at "H" level under normal conditions. Note: The input circuit of the RESET pin operates on a VCPU power supply, and the input voltage level is 0 V~VCPU.
Note: The power-on reset circuit operates on power startup of the VCPU power supply. Note: The LCD common output and the segment output will be fixed at "L" level during system reset and during the subsequent standby period. Note: It is necessary to initialize any internal port shown in the above-mentioned I/O map that has not been initialized after system reset. The mark on the I/O map shows a port or bit that is set to "0" after system reset, while the mark shows a port or bit that is set to "1". No mark shows a port or bit that is unfixed.
I/O
L2F OUT2
L2D
Y1
Y2
Y4 MUTE control
Y8
8
IMUTE POL Break
MUTE
After system reset, unmarked port is unfixed.
ENA
After system reset, this port is set to "1".
After system reset, these ports are set to "0"
VDD pin (Note) VCPU pin (Note)
GND GND
RESET pin
A crystal oscillator stops during the reset from a reset pin.
GND
XOUT pin
Standby (about 100 ms) CPU operation CPU operation Standby (about 100 ms) CPU operation Standby (about 100 ms)
Internal reset signal
Reset
< Timing of Operation >
Note: If the VDD power supply voltage falls below 0.9 V or the VCPU power supply voltage falls below 1.2 V, set to clock stop mode and operate the reset function. The VCPU power supply voltage will be reset when the power supply is restarted (power-on reset). Note: VCPU pins are usually supplied from doubler voltage VDB pins. Refer to the backup mode item.
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System clock control circuit
The system clock control circuit consists of a clock generator, clock generator control port, timing generator and backup mode control circuit.
Clock generator CO XOUT1 75 kHz X IN1 300 600 kHz CI XOUT2 Peripheral timing generator High-speed oscillator CPU timing generator Low-speed oscillator Clock generator control port (L15F) Backup mode control circuit
CI
Peripheral clock CPU clock
XIN2
VDD
Note: It is necessary to use a crystal resonator with a low CI value and favorable startup characteristics. Note: Adjust and determine the external resistance and capacitor constant to match the crystal resonator actually used. Note: The low-speed oscillator and high-speed oscillator are equipped with a built-in Schmitt circuit. Note: The power supply of the low-speed oscillator and high-speed oscillator uses a VDD pin.
1. Clock generator
The clock generator circuit generates the basic clock used as the standard for the system clock supplied to a core-based CPU and peripheral hardware. The circuit incorporates low-speed and high-speed oscillators, with a 75 kHz crystal resonator connected to the XIN1 and XOUT1 pin and a 300 to 600 kHz ceramic resonator or a crystal resonator connected to the XIN2 to XOUT2 pin. The CPU clock and doubler clock (VDB doubler or doubler for VT) can be converted to a high-speed oscillation clock through programming. Since items such as the timer and reference frequency utilize the 75 kHz clock during this time, the timer duration measurement and PLL are unaffected.
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2. Clock generator control port
The clock generator control port controls the low-speed and high-speed oscillators.
Y1 L15(F)
INV ON
Y2
OSC2 ON
Y4
CK SEL
Y8
*
Selection of CPU clock
0: Low-speed oscillator 1: High-speed oscillator 0: Oscillator stop 1: Oscillator 0: Constant-current system 1: Inverter system
High-speed oscillator control Selection of low-speed oscillator
The OSC2ON bit controls the on/off setting of the high-speed oscillator. If this bit is set to "1", the high-speed oscillator is enabled and oscillation is started. The CK SEL bit converts the CPU operation clock to a low-speed or high-speed oscillator clock. After reset, the CPU operates with a 75 kHz low-speed clock. When the high-speed clock is to be used, conversion to the high-speed clock takes place after the OSC2 ON bit is set to "1" and the high-speed oscillator frequency is stabilized. The INV ON bit can be used to change the circuit type of the 75 kHz low-speed oscillator. This is usually set to a constant-current type.
Note: The high-speed oscillator clock can be used as the doubler clock for the VDB pin or doubler clock for the VT (DDCK1/DDCK2). Note: CK SEL bit control is restricted to conversion of the CPU operation clock and does not affect items such as PLLs and timers. Note: The circuit type of the 75 kHz low-speed oscillator is used for the constant-current system. If the crystal oscillator circuit is set to an inverter type, its output level rises. This circuit type should only be used to investigate whether or not the tuner characteristic of the crystal oscillator has been affected.
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DC/DC converter for CPU
The device incorporates a DC/DC converter for the CPU power supply. The CPU doubler circuit comprises a charge pump system utilizing a capacitor. There is a built-in clamp control function, for which an electrical potential of 2.0, 2.5 and 3.0 V can be set through programming. The capacitor-utilizing charge pump system supplies a VDD level charge between the C1 and C2 pins, and a doubler potential twice the VDD potential is output to the VDB pin. Note that, if twice the voltage of the VDD pin decreases following clamp setting using this method, the doubler potential also decreases. Three types of 1/2 frequency can be selected for the doubler clock: 37.5 kHz, 75 kHz, and a high-speed oscillation clock. After reset, a frequency of 37.5 kHz is output. Set the doubler clock to the required doubler capability. The doubled VDB potential is supplied to the A/D converter and the VEE constant-voltage circuit. The VDB potential is usually supplied to the VCPU pin through a Schottky diode.
Y1 L14(8)
VC0
Y2
VC1
Y4
CLAMP
Y8
OSC2
Doubler clock frequency selection for doubler
OSC2 ON (L15(F)-Y2) OSC2
Doubler Clock Frequency for the CPU Low-speed oscillator clock (75kHz)x1/2
Doubler Clock Frequency for the LCD Driver Same as left
* 0 1
0 1 1
Low-speed oscillator clock (75kHz) Low-speed High-speed oscillator clock (300600kHz)x1/2 oscillator clock
Clamp function control 0: OffVDD x 2 1: On Clamp voltage control Note: This becomes effective only when the clamp function is ON. VC0 0 0 1 1
VC1
Clamp voltage Prohibition 2.0V 2.5V 3.0V
0 1 0 1
Note: If the OSC2 bit is set to "1", the doubler clock for the LCD driver is also changed simultaneously.
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Doubler clock CLAMP
Doubler circuit
Internal reference voltage
Internal doubler voltage (A/D converter, constantvoltage C2 circuit)
VDD 2 0.1 F 10 F
C1 3
VDB Doubler voltage 0.1 F 10 F
4
Example of an Application Circuit for a Charge Pump Doubler System Utilizing a Capacitor
Note: The VDB pin is fixed at the VDD pin level while the clock stop instruction is being executed.
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Constant-voltage circuit (VEE)
There is a built-in constant-voltage circuit (VEE) to provide the reference voltage of the LCD driver and DC/DC converter for the VT and for the CPU and A/D converter. The constant-voltage circuit utilizes the doubler VDB pin power supply for the CPU and outputs a constant voltage of 1.5 V from the VEE pin. There is a constant-voltage compensation data port for rectifying the constant-voltage value VEE, and voltage can be rectified per 20 mV. Do not set this port through programming as correction data is usually determined at the time of shipment.
Y1 L16(E)
TR0
Y2
TR1
Y4
TR2
Y8
TR3
The constant-voltage rectify data Note: After system reset, this serves as the port for data rectification so that VEE is set to 1.5 V at the time of shipment. For this reason, do not access this port. Note: During reset or a clock stop, the VEE pin becomes high impedance.
LCD driver doubler circuit (VLCD)
There is a built-in doubler circuit for LCD drivers (VLCD) that acts as an LCD driver power supply. The doubler circuit for LCD drivers outputs a 3 V constant voltage doubled from a 1.5 V constant voltage through the capacitor-utilizing charge pump system doubler.
1.5 V constantvoltage circuit
37.5kHz or 75kHz
Doubler circuit
To LCD driver
VEE
C3 9 6
C4 7
VLCD
8
0.47 F
0.1 F
0.1 F
Note: During reset or a clock stop, the VLCD pin outputs the VCPU level. Note: The VLCD doubler potential is used for the power supply in the I/O port, etc. Note: The doubler clock can use 37.5 kHz or 75 kHz (OSC2 bit).
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Backup mode
Backup mode decreases the operating current and holds data memory and other registers. Backup mode can be implemented through programming-based backup or hardware-based backup. For programming-based backup, three types of backup mode are possible through the executing of CKSTP or WAIT instructions. For hardware-based backup there are two types of function: a decreased voltage detection function and a power-off backup function. When the VDD pin power supply falls to the decreased voltage detection setting potential (VDD = 0.85 V 1.225 V), a decrease voltage detection function stops the CPU temporarily and prevents incorrect operation of the CPU. During this time, the operational status of such items as the LCD driver, I/O ports, and PLL is held. If the VDD pin level is set to approximately 0.5 V or less, the power-off backup function will stop functions such as LCD driver, I/O port, and PLL operations; reduce the only power supply for the CPU (VCPU pin) to a low consumption current (0.5 A or less); and hold memory contents and the status of other registers.
1. Clock stop mode
Execution of the CKSTP instruction actuates clock stop mode. Clock stop mode suspends system operations while maintaining the internal status immediately prior to suspension. At this time, the VDD, VPLL and VCPU pin power supplies change to low consumption current (10 or less A); crystal oscillation stops; the LCD indication output pin and CMOS output port are fixed to the "L" level; and the N-ch open drain pins are all set to the OFF (high-impedance) state automatically. The power supply of the VDD and VPLL pins can be lowered to the OFF state, and the power supply of the VCPU pin power supply can be lowered to 0.75 V. Clock stop is released under the following conditions: 1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to input. (Refer to the section on I/O ports.) 2) If the VDD power supply pin is changed from the off to the on state (at approximately 0.5 V or more) when the VDD power supply break is enabled (BRAEK ENA bit (L11(F)) = "1"). Release of clock stop mode causes the next address to be executed after 100 ms of standby time have elapsed.
Note: The PLL changes to the off state during execution of the CKSTP instruction.
Break pin High impedance XOUT1 pin CPU operation Clock stop Standby (about 100 ms) CPU operation
CKSTP instruction
Executing of CKSTP instruction
Executing of CKSTP instruction
Example of Operation Timing Using a Break Pin
Note: Clock stop mode is actuated on execution of the CKSTP instruction. Note: When break pin input is set, it is necessary to read this input state before execution of the CKSTP instruction.
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VCPU pin GND VDD pin When a voltage of approx. 0.5 V or more is impressed, it is released. GND
XOUT1 pin CPU operation CKSTP pin Executing of CKSTP instruction Executing of CKSTP instruction Clock stop (backup) Standby (about 100 ms) CPU operation Clock stop
Example for Operating Timing by Power Supply Pin
Note: Release of the CKSTP instruction through on/off of the VDD power supply pin requires the BREAK ENA bit (L11(F)) to be set to "1". When this function is enabled, about 10A will be consumed in the VCPU pin if voltage is applied through the VDD pin during CKSTP instruction execution. For this reason, this function should be prohibited if voltage is always impressed through the VDD pin power supply. Note: It is necessary to retain the potential of the VCPU pin. Provide backup using a capacitor or similar means. Note: Reset occurs if the VCPU pin level (typ: 0.3 V) falls to 0.75 V or below and the voltage is then applied (power-on reset).
2. Wait mode
Wait mode suspends system operations, maintains the internal status immediately prior to suspension and decreases current consumption. This mode stops at the address for the execution of the WAIT instruction on execution of hard and soft wait. On cancellation of wait mode, the next address is executed immediately, with no standby interval. (1) SOFT WAIT mode Only CPU operations within the device are suspended when a WAIT instruction is executed in which [P = 0H] has been specified in the operand. The crystal resonator and other elements will continue to operate normally at this time. SOFT WAIT mode is efficient in reducing current consumption during clock operations when used in programs that include clock functions. The wait status applies whenever the WAIT instruction is executed. Wait mode is canceled on the following conditions: 1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to input. (Refer to the section on I/O ports.) 2) When the 2 Hz Timer F/F is set as "1"
Note: The backup state applies if the VDD power supply pin goes off in wait mode when the VDD power supply is enabled (BRAEK ENA bit (L11(F)) = "1"). The state is released when the power supply is turned on (at approximately 0.5 V or more). At this time, the CPU starts up after 100 ms of standby time have elapsed. Note: Current consumption will vary depending on the execution time of the CPU operation.
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(2) HARD WAIT mode The operations of all elements, with the exception of the crystal resonator and doubler operating (VDB / VLCD pin), can be suspended by execution of a WAIT instruction in which [P = 1H] has been specified in the operand. This enables even greater levels of current consumption reduction than SOFT WAIT mode. This suspends the CPU operation. During hard wait mode, the state of the output port is maintained and all LCD output pins are fixed at the "L" level. The wait status is assumed whenever the WAIT instruction is executed. Wait mode is canceled on the following conditions: 1) If there is a change in the input state of an I/O port (I/O ports 3, 4, 6, and 8) that has been set as a break pin and to input. (Refer to the section on I/O ports.) 2) If the VDD power supply pin is changed from the off to the on state (at approximately 0.5 V or more) when the VDD power supply break is enabled (BRAEK ENA bit (L11(F)) = "1").
Note: Wait mode is also released when the VDD power supply pin in wait mode is changed from the off to the on state (at approximately 0.5 V or more) when the VDD power supply break has been enabled (BRAEK ENA bit (L11(F)) = "1"). Note: The PLL OFF status will be assumed during wait mode. Note: During wait mode, the power supply doubler circuit (VDB pin), the constant-voltage supply circuit for the LCD (VEE pin) and the doubler circuit for the LCD ( VLCD pin) continue to operate.
3.
Backup mode by hardware
The backup mode by hardware detects the power supply voltage level of a VDD pin and actuates backup mode. There are two types of backup function by hardware: a decreased voltage detection function and a power supply off detection function. (1) Decreased voltage detection function The decreased voltage detection function detects the VDD pin level, suspends the operation of the CPU and prevents incorrect operation of the CPU. If the VDD pin level falls below the decreased voltage detection setting (VDD = 0.85V - 1.225V) potential when the detected decrease voltage function is enabled, CPU operation will be suspended; and if the VDD pin again rises above the set voltage, the CPU will restart. Although the CPU stops, other functions continue to operate normally. Decreased voltage detection operation is performed at intervals. The frequency of detection can be selected through programming, with detection being performed at a rate of once every two instructions or 16 instruction cycles. Select according to power consumption and speed of power supply variation. The detection voltage can be set to an interval of 25 mV within the range of VDD = 0.85 V 1.225 V. Set according to the specification. Since suspension of CPU operation can be prohibited, it is also possible to detect residual battery level between 0.85 V and 1.225 V by varying the detection setting voltage and detecting the detection flag. In this case, execute a backup instruction after detection of the minimum voltage level to prevent incorrect operation of the CPU. Where interrupt is permitted, the interrupt will be issued if the VSTOP F/F bit is set to "1". If interrupt is received, the program will branch to 0003H address. Moreover, PLL off-mode can be actuated during decreased voltage detection. Therefore the PLL can be quickly suspended should the voltage drop. The VSTOP F/F bit enables detection of suspension or of a fall below the detection voltage. Upon detection this bit is set to "1" and will be reset by execution of flag reset (STOP F/F Reset = "1"). Through programming, therefore, it is possible to make various operation settings for when a decrease in the VDD potential (battery voltage) occurs.
Note: Both serial interface and timer port are used for the interrupt function of the decreased voltage detection circuit. When this interrupt is used, the interrupt function of the serial interface and the timer port cannot be used.
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(2) Detected power supply OFF function Detected power supply OFF function detects the fact that the power supply is off during battery exchange or similar procedures and actuates the backup state of the CPU circuit (VCPU pin) to keep it on hold. If the detected power supply off function is enabled (BRAEK ENA bit (L11(F)) = "1"), the VDD pin level is about 0.5 V or less and all functions stop. At this time, the VCPU pin power supply changes to low current consumption (0.5 A or less); the LCD output pin and CMOS output port change to "L" level; the N-channel open-drain pins are all automatically fixed to the off (high-impedance) state; and the PLL changes to off mode. If the power supply is switched on again, the CPU will operate after a standby interval of 100 ms. The VDD OFF F/F bit enables detection of whether the power supply has been switched off.
Note: Set the VDD pin level to GND level during power supply off. If VDD level potential remains, current will be consumed by the VCPU pin. Note: The BRAEK ENA bit (L11(F)) permits VDD power supply break and power supply off detection function. Note: Use this function together with the decreased voltage detection function.
(3)
Backup control register by hardware Decreased voltage detection and power supply off detection function control are accomplished through access of the decreased voltage control port (L11(E), L11(F)); the decreased voltage detection setting data port (L16(D), K11(D)); and the flag register (K26).
L11(E) (decreased voltage control 1) Y1
WAIT ENA
Y2
PLLoff ENA
Y4
STOP ENA
Y8
*
Permission for decreased voltage detection function 0: Prohibition Decreased voltage detection function suspended 1: Enable Decreased voltage detection function operating
Permission for PLL stop function on decreased voltage detection 0: Prohibition 1: Enable PLL off mode and PLL stop are executed when decreased voltage is detected.
Permission for CPU stop function on decreased voltage detection 0: Prohibition 1: Enable CPU stops when decreased voltage is detected.
(Note) Settings become invalid if the decreased voltage detection function is suspended. Note: If the decreased voltage detection function is not being used, set the WAIT ENA bit to "0" for reduced consumption current.
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L11(F) (decreased voltage control 2) Y1
STOP F/F Reset
Y2
INT LB SEL
Y4
TIM SEL
Y8
BREAK ENA
Power supplies off break enable/power off function enable 0: Prohibition 1: Enable Function stop Function operation
(Note) If not using this function, set this bit to "0" for consumption current reduction. Selection of decreased voltage detection operating timing 0: Detection is performed at a rate of once every 2 instruction cycles. 1: Detection is performed at a rate of once every 16 instruction cycles. (Note) If this bit is set to "1", the consumption current of this function can be decreased. Permission of interruption by decreased voltage detection (refer to the item on the interruption function) 0: Serial interface or timer port 1: Decreased voltage detection Reset execution of decreased voltage detection F/F and power supply OFF F/F: Every time it is set to "1" decreased voltage F/F and power supply OFF detection F/F are reset simultaneously.
Y1
Y2
Y4
VDD OFF F/F
Y8
0
K26
STOP F/F
Power supply off detection flag 0: Power supply off not detected 1: Power supply off detected Decreased power supply detection flag 0: Over the decreased voltage detection setting voltage 1: Under the decreased voltage detection setting voltage
Note: The STOP F/F changes to the reset state, with a CPU standby interval (100 ms), after system reset; after release of the CKSTP instruction; and after detection of power off using the power-off detection circuit.
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Y1 L16(D) 11(D) TR0 Y2 TR1 Y4 TR2 Y8 TR3 TR3 TR2 TR1 TR0 Data (HEX) 0 Decreased voltage detection setting data 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 A B C D E F Decreased voltage detection voltage (V) 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225
Note: Decreased voltage detection voltage detected VDD pin level. Note: Any fall below the decreased voltage detection voltage will cause the STOP F/F to be set to "1"; and the CPU will stop as a result of decreased voltage detection. Note: The decreased voltage detection value is a standard value. The constant voltage of the VEE pin is used as the standard voltage of the decreased voltage detection circuit. Since this VEE voltage varies from product to product, the decreased voltage detection value also varies at the same time. Note: If a high-speed oscillator clock is being used for the CPU clock, assign the decreased voltage setting data to between 0H 6H (0.85 V 1.00 V). Do not make any other setting.
(4)
VCPU Pin VCPU
Decreased voltage detection, power supply off detection timing

GND
VDB Pin VDB

GND
Decreased voltage setting voltage

VDD Pin VDD

GND
Backup operates on a setting of approximately 0.5 V or less 0.5V but will be canceled if the voltage exceeds this value.
CPU CPU operation
CPU CPU operation CPU CPU stop CPU CPU stop (Note 1)
Flag reset execution (execution of ResetF/F Reset=1) (STOP F/F STOP = 1)
Power supply OFF detection (Backup)

XOUT1 XOUT1 Pin

Stand-by (100ms) (About 100 ms)
CPU CPU operation
CPU stop CPU
CPU CPU operation

VDD OFF F/F
When interrupt has been permitted, interrupt is issued using STOP F/F. STOP F/F
Example of timing operation
Note 1: Decrease voltage is detected and CPU operation is suspended. It is then necessary to detect the VDD power supply voltage. When performing power off, therefore, ensure that the fall time from the decreased voltage detection voltage to the detection of the power supply voltage (approximately 0.5 V) is equal to or greater than the timing period for operation of decreased voltage detection (i.e., two or 16 instruction cycles). Failure to do so will cause CPU malfunction. Note 2: STOP F/F is reset during standby time.

STOP F/F

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(5) Backup circuit
50 VPLL
Reset input
62 RESET 10 k VDD 2 C1 3 C2 VDB 4 5 1 k Schottky diode 0.1 F 10 F 0.1 F 470 F (Capacitor for backup)
VCPU 10
VCPU 10
POWER
0.47 F
0.1 F
10 F
Example Capacitor Backup Circuit (1)
50 VPLL
Reset input
62 RESET
10 k
VDD 2
C1 3
C2 VDB 4 5
0.47 F POWER
Schottky diode
1 k
Break input pin
Release signal input
0.1 F
10 F
0.1 F
10 F
Example Battery Backup Circuit (2)
Note: If backup operation using a CKSTP/WAIT instruction is available, use release signal input to perform the release operation as necessary. Moreover, on execution of the CKSTP command, connect an external capacitance of 4.7 mF or more for the VCPU pin resistance as in Example Capacitor Circuit (2) above. Note: The diode shown in the circuit diagrams should be a Schottky diode with a low VF and a small reverseleakage current. Recommended diodes: 1SS357, 1SS393 Note: Set the backup capacitor capacity value according to the required backup time. Note: The "H" level of reset input requires the application of a VCPU level voltage. Therefore set high impedance at the time of reset off. Note: The VCPU pin power supply is a logic power supply with a timing circuit, ALU, data memory and all registers. The VCPU pin power supply should usually be retained at the time of backup.
0.1 F
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4. PLL OFF mode
The PLL can be turned on or off depending on the contents of the reference selection port. If all the contents of the reference selection port are set to "1", PLL off mode applies. (Refer to the section on the reference frequency divider.) When the INH ENA bit is set to "1", the PLL can be turned on or off with the INH pin. The INH pin input serves as PLL off mode at "L" level, and serves as PLL on mode on the "H" level. As a result, it is possible quickly to set PLL off mode when changing batteries These data are accessed by an OUT1 instruction specifying 9h for the data select port (K/L1A) and [CN = 5H] for the operand. Moreover, PLL off mode can be set by decreased voltage detection. (Refer to the section in 3. Backup mode by hardware.) The VPLL pin serves as low consumption current at the time of PLL off mode. Moreover, the power supply for a VPLL terminal can be turned off at this time.
Y1 Y2
0
Y4
0
Y8 INH
ENA
L15(9)
0
Enable to the PLL control by INH pin 0: Prohibition 1: Enable P4-1/ INH pin
"L": PLL off mode "H": PLL on mode
Note: PLL off mode applies during clock stop mode, hard wait mode, and when power off occurs as a result of the power supply off detection function. Note: The VPLL pin power supply is a prescaler and programmable counter power supply. When only the VPLL pin power supply is turned off, the setting method of dividing frequency and the value of dividing frequency are maintained because the VCPU power supply is used. Moreover, when the PLL is on, the level of the applied VPLL pin voltage can supply power to the PLL regardless of the VDD pin or the potential of the VCPU pin. Note: INH input pin is used together with the P4-1 pin. The functionality becomes effective when the INH input is enabled, and the external interrupt function (INTR2) and the break function are enabled. Moreover, the input state can be judged by reading the P4-1 input data of an I/O Port 4 input port (K33). Note: The I/O port control port of P4-1 pin becomes invalid and is forced to enter the input state if INH input has been enabled. Note: Set the Y1/Y2/Y4 bit of the above-mentioned port to "0".
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Register port
The G-register, data register and DAL address register, which were mentioned in the description of the CPU, are arranged on the I/O map, and treated as one of the internal ports. The carry flag can also be accessed from an I/O map. (Refer to the section on I/O access of the stack register.) Of these registers, the G-register, the carry flag, and the data register have a four-page interrupt stack register corresponding to the four stack levels. On execution of interrupt processing, these contents are automatically stored in the interrupt stack register together with the contents of data selection and automatically returned on execution of an RNI instruction. (Refer to the section on the interrupt stack register.)
1. G-register (L/K18, L/K19)
This register addresses the row addresses (DR = 04H ~ 1FH) of the data memory during execution of the MVGD instruction and MVGS instruction. The register is accessed with the OUT1/IN1 instruction for which [CN = 8H ~ 9H] has been specified in the operand. Moreover, if the STGI instruction is used, data can be set to this register with a single instruction. This register has a four-level interrupt stack register. On the issuing of interrupt, the contents of the G-register are evacuated to the interrupt register specified by the interrupt stack pointer and returned by the RNI instruction.
Note: The contents of this register are only valid when the MVGD instruction and MVGS instruction are executed and are ineffective when any other instruction is executed. Moreover, this register is unaffected by the MVGD instruction and MVGS instruction. Note: All of the data memory row addresses can be specified indirectly by setting data 00H to 1FH in the Gregister (DR = 00H ~ 1FH). Note: It is possible to rewrite and reference the contents of the interrupt stack registers ISRG0 ~ ISRG4 (L/K10(8), L/K10(9)) through programming.
L/K10(6) Y1 ISP0 Y2 ISP1 Y4 */0 Y8 */0
Interruption stack pointer Interrupt stack pointer Interrupt stack pointer L/K10(8) Page 0 ISRG0 ISRG1 ISRG2 ISRG3 1 2 3 Page 0 L/K10(9) ISRG4 1 2 3 */0 */0 */0
Interrupt stack register Interruption stack register At the time of RNI At the time of interrupt At the time of interrupt At the time of interruption instruction execution processing execution processing execution processing execution
Y1 L/K18 G0
Y2 G1
Y4 G2
Y8 G3 L/K19
Y1 G4
Y2 *
Y4 *
Y8 *
G-register
Specification of the low address of a data memory G4 0 G3 0 0 0 G2 1 1 1 G1 0 0 1 G0 0 1 0 DR 04H 05H 06H
STGI instruction 0 1 2 3 4
0 0 1
*
1
1
1
1
1FH
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2. Data register (L/K1C ~ L/K1F), DAL address register (L/K11(0) ~ L/K11(3)) and control bit
The data register is 16-bit register for which the program memory data is loaded when the DAL instruction and DALR instruction are executed. The contents of this register are loaded into the data memory in 4-bit units with the execution of the OUT1/IN1 instructions for which [CN = CH ~ FH] has been specified in the operand. This register can be used for loading LCD segment decoding operations, radio band edge data and data related to binary-to-BCD conversion. The data register has a four-level interrupt stack register. On the issuing of interrupt, the 16 data register bits are evacuated to the interrupt register specified by the interrupt stack pointer and returned by the RNI instruction.
L/K10(6) Y1 ISP0 Y2 ISP1 Y4 */0 Y8 */0
Interrupt stack pointer Interruptionstack pointer Interrupt stack register Interruption stack register
Y1
Y2
Y4
Y8
L/K10(C) ISRd0 ISRd1 ISRd2 ISRd3 L/K10(D) ISRd4 ISRd5 ISRd6 ISRd7 ISRd1 ISRd1 0 1
L/K10(E) ISRd8 ISRd9
L/K10(F) ISRd1 ISRd1 ISRd1 ISRd1 2 3 4 5 Page 0 Page 1 Page 2 Page 3
At time of of interrupt At the the timeinterruption processing execution processing execution
At the time of RNI instruction execution DAL address register (AR) Y1 L/K11 (0) (1) (2) MVAR instruction execution Data select L/K1A (3) AR0 AR4 AR8 AR12 AR1 AR5 AR9 AR2 AR6 AR10 AR3 AR7 AR11 0 Y2 Y4 Y8
Data register data (16 bits) Data register data( 16 bit)
LSB L/K1C L/K1D L/K1E L/K1F
Y1 0 4 8 12
Y2 1 5 9 13
Y4 2 6 10 14
Y8 3 7 11 15
AR13 TROM
MSB DALR instruction DAL instruction /DAL instruction execution Program memory 16 bit data 16-bit data
DALR instruction indirect specification address
Note: Whenever it executes a DALR instruction,
Program memory area (ROM)
Note: Each time a DALR of the DAL address register +1 increment instruction is executed, the
(AR) is done. DAL address register (AR) is incremented by +1. DAL instruction indirect specification address (ADDR3,r) ADDR3,r
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The DAL address register (AR) is a register that specifies the program-memory-indirect when the DALR instruction is executed with the 16-bit register. There are two types of commands that load the program memory data: the DAL instruction and the DALR instruction. For the DAL instruction, the contents of the (six-bit) ADDR3 in the operand and of the general register (r) become the reference address of the program memory. For the DALR instruction, the 14 bits of the DAL address register become the reference addresses. When the DAL instruction is executed, the program memory area (0000H ~ 03FFH) becomes the reference area. All the areas in the program memory area can be referred to by executing the DALR instruction. Whenever the DALR instruction is executed, the content of the DAL address register is increased by +1. Therefore data can be continuously loaded. Moreover, the content of the data register can be transmitted to the DAL address register in 14 bits with one instruction by executing the MVAR instruction. The contents of the DAL address register can be accessed in four-bit units on execution of an OUT1/IN1 instruction for which [CN = 1H] is specified in the operand. DAL address register port is divided and indirectly specified with the data selection port (L1A) and set. The data of the specified port to be set beforehand is set and the data port corresponding to it is accessed. Each time the data select port (L/K11) is accessed it is increased by +1. Therefore the data can be continuously accessed after setting up a data selection port.
Note: The DAL address register is valid only when the DALR instruction is executed, and is ineffective when any other instruction is executed. Moreover, the DAL address register is unaffected by the DAL instruction. Note: This product has 8 k steps of ROM capacity; if 2000H ~ 3FFFH is specified in the DAL register and the DALR instruction is executed, the contents of the data register will become indeterminate. Note: It is possible to rewrite and reference the contents of the interrupt stack registers ISRd0~ISRd15 (L/K10(CF)) through programming.
3. Carry flag (L/K1B)
The carry flag is set when either Carry or Borrow occurs in the result of the calculation instruction execution and is reset if neither of these occurs. This carry flag is accessed with an OUT1/IN1 instruction for which [CN = BH] has been specified. The carry flag contains a four-level interrupt stack register. When an interrupt is issued, this bit is evacuated to the interrupt register specified by the interrupt stack pointer, and is returned with the RNI instruction.
L/K10(6) Y1 ISP0 Y2 ISP1 Y4 */0 Y8 */0
Interrupt stack pointer Interruption stack pointer
L/K10(B) Page Page 0 ISRCA 1 2 3
Interrupt stack register Interruption stack register At the time of RNI instruction execution At the time of interruption At the time of interrupt processing execution processingexecution Y1 Y2 Y4 Y8
*/0
*/0
*/0
L/K1B
Ca
*/0
*/0
*/0
Carry flag Carry flag
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Stack register
The stack register consists of an address stack register (ASR) and an interruption stack register (ISR). A stack register is used when subroutine call instructions and interrupt processing are executed. Interrupt stack registers comprise 26 Gregister, data select, carry flag, and data register bits, as described in the register port item and I/O map. These stack registers are arranged on an I/O map, and are read from and written into with input and output instructions.
1. Address stack register (ASR)
The address stack register (ASR) is a 14 bit x 16 page register. When the subroutine call instruction and the interrupt processing are executed, the value increased by +1 of the content of the program counter, i.e., the return address, is stored in the address stack register. When interrupt processing is executed, a return address that is an interrupt processing execution address is stored in the address stack register. This register consists of 16 pages and is specified by four address stack pointer (ASP) bits. If transmitted to an address stack, an address stack pointer will be adjusted by -1. Then, after processing of the subroutine or interrupt, the address stack pointer is increased by +1 with the RN/RNS instruction or the RNI instruction, the content of the address stack register is transmitted to the program counter, and the program returns from the subroutine or the interrupt processing. An address stack register comprises 16 pages and features 16 nesting levels. The address stack register and the address stack pointer are arranged on the I/O map, and their contents can be referred to or rewritten.
L/K10(0) Y1 ASP 0 Y2 ASP 1 Y4 ASP 2 Y8 ASP 3
Address stack pointer
At the time of CAL instruction // interruption processing execution instruction interrupt processing execution At At the time of RN/RNS/RNI instruction processing execution
Address stack register Address stack register Y1 Y2 Y4 Y8
(ASP)ASP+1 (ASP)ASP-1
Page specification
L/K10(2) ASR0 ASR1 ASR2 ASR3 L/K10(3) ASR4 ASR5 ASR6 ASR7 L/K10(4) ASR8 ASR9 ASR10 ASR11 L/K10(5) Page 0 ASR12 ASR13 */0 */0
ASR(PC)+1
Program counter (PC: 14 bit) Program couter (PC : 14 bit)
At the time of CAL instruction At the time of CAL instruction / / interrupt processing execution interruption processing execution
Program memory area ROM (ROM)
PC(ASR) At the time of RN/RNS/RNI instruction processing execution
Page 1 Page
Page 2 Page 3 Page 3
Page Page 15
Note:
The program memory area consists of 16 kilobytes, and 13 bits are used. Therefore set the most significant bit (ASR13) to "0".
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2. Interrupt stack register (ISR)
The interrupt stack register (ISR) is a 14 bit x 16 page register. When interrupt processing is executed, the contents of the 26-bit G-register, data selection, carry flag, and data register are stored automatically. This register consists of four pages and is specified with a two-bit interrupt stack pointer (ISP). When interrupt is generated, the G-register and other 26-bit register contents are transmitted to the interrupt register. Simultaneously, the interrupt stack pointer is adjusted by -1. When the RNI instruction is executed after the interrupt processing is finished, G-register and other 26-bit register contents are returned and the interrupt stack pointer is increased by +1. In this way, the interrupt stack register (ISR) is used as a save register for when interrupt occurs. The Interrupt Stack register consists of four pages, and there are four interrupt stack levels. The interrupt stack register and the interruption stack pointer are arranged on the I/O map, and their contents can be referred to and rewritten.
L/K10(0) Y1 ISP0 Y2 ISP1 Y4 */0 Y8 */0
Interrupt stack pointer
At the time of interruption processing execution (ISP)ISP+1 (ISP)ISP-1 RNI instruction processing execution Interrupt stack register Y1 Y2 Y4 Y8 L/K18 Y1 G0 Y2 G1 Y4 G2 Y8 G3
L/K10(8) L/K10(9) Page specification L/K10(A) L/K10(B) L/K10(C) L/K10(D) L/K10(E)
ISRG0 ISRG1 ISRG2 ISRG3 ISRG4 */0 */0 */0
ISRS0 ISRS1 SEL4 ISRS2 ISRCA */0 */0 */0
*/0 */0 L/K19 G4 */0 At the time of interruption processing execution L/K1A SEL1 SEL2 SEL4 SEL8 L/K1B L/K1C L/K1D L/K1E RNI instruction processing execution L/K1F CA d0 d4 d8 d 12 */0 d1 d5 d9 d 13 */0 d2 d6 d 10 d 14 */0 d3 d7 d11 d15
ISRd0 ISRd1 ISRd2 ISRd3 ISRd4 ISRd5 ISRd6 ISRd7 ISRd8 ISRd9 ISRd1 ISRd1 0 1
L/K10(F) ISRd1 ISRd1 ISRd1 ISRd1 4 5 2 3 Page 0 Page 1 Page 2 Page 3
G-register Data select Carry flag Data register
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3. I/O access of a stack register
The stack register is arranged in the I/O map. Therefore reading the state of the stack register and rewriting data are possible. The contents of an address stack pointer (ASP) or an interruption stack pointer (ISP) can also be accessed. These data are accessed with an OUT1/IN1 instruction for which [CN = 0H] is specified for the operand, and divided and arranged by the data selection function. The address stack register and the interrupt stack register have 16 and four pages respectively. When these ports are accessed with the I/O instruction, the page is specified before the stack register is accessed. The address stack selection specifies the page of the address stack register. The interrupt stack selection specifies the page of the interrupt stack register. Rewriting of address stack registers is set from low-ranking bit, while the 14 address stack register bits are updated by accessing high-ranking bits. Therefore care is required: it is still necessary to access the high-ranking bits even when only low-ranking bits are being changed.
L/K10(0) Y1 ASP 0 Y2 ASP 1 Y4 ASP 2 Y8 ASP 3
L/K10(0) Y1 ISP0 Y2 ISP1 Y4 */0 Y8 */0
Address stack pointer nesting level is setting / detectable.
Interrupt stack pointer nesting level is setting / detectable.
L/K10(1) Y1 ASS 0 Y2 ASS 1 Y4 ASS 2 Y8 ASS 3
L/K10(7) Y1 ISS0 Y2 ISS1 Y4 */0 Y8 */0
Address stack select
Interrupt stack select Interrupt stack register Y8 L/K10(8) Y1 Y2 Y4 Y8
Address stack register Y1 Y2 Y4
L/K10(2) ASR0 ASR1 ASR2 ASR3 L/K10(9) L/K10(3) ASR4 ASR5 ASR6 ASR7 L/K10(A) L/K10(4) ASR8 ASR9 ASR10 ASR11 L/K10(5) Page 0 1 2 3 L/K10(D) L/K10(B) ASR12 ASR13 */0 */0 L/K10(C)
ISRG0 ISRG1 ISRG2 ISRG3
ISRG4
*/0
*/0
*/0
ISRS0 ISRS1 SEL4 ISRS2
ISRCA
*/0
*/0
*/0
ISRd0 ISRd1 ISRd2 ISRd3
ISRd4 ISRd5 ISRd6 ISRd7 ISRd1 ISRd1 0 1
L/K10(E) ISRd8 ISRd9 15
L/K10(F) ISRd1 ISRd1 ISRd1 ISRd1 2 3 4 5 Page 0 1 2 3
Note: The program memory area is 16 kilobytes and 13 bits are used. Therefore it is necessary to set the most significant bit (ASR13) of the address stack to "0".
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Interrupt function
There are six types of peripheral hardware for which the interrupt function can be utilized: the INTR1 terminal, the INTR2 terminal, the timer port, the serial interface, the timer counter, and the decreased voltage detection circuit. This peripheral hardware will issue an interrupt request signal if certain conditions are satisfied. On reception of an interrupt, the data for the G-register, data selection, carry flag, and data register are shunted to an interrupt stack register, and the return address is shunted to the address stack register. The process then branch to the vector address determined by the various interrupt factors and starts the related interrupt processing routine. The interrupt routine requires preprocessing and post-processing to enable recovery of the same operational state that prevailed when the interrupt occurred. On interrupt, the G-register, data selection, carry flag, and data register are automatically shunted to the interrupt stack register; they are returned from the interrupt stack register on execution of the return instruction for interrupt (RNI). Registers used with other ALU and memory data that cannot be broken must be shunted to and recovered from the data memory for interrupt through the use of programming. Interrupt priority can be set through programming. During interrupt processing, processing of an interrupt with a priority lower than the interrupt currently being processed is prohibited. The data of the interrupt stack register and the address stack register return on executing of the return instruction for interrupt (RNI), and the interrupt processing ends.
1. Interrupt control circuit
The interrupt control circuit consists of an interrupt enable flag, interrupt latch, and interrupt priority circuit block. These performs are set and controlled with OUT2/IN2 instructions. (1) Interrupt enable flags The interrupt enable flags consist of individual enable flags corresponding to the four interrupt factors, and a master enable flag, which permits and prohibits the whole interrupt processing. The individual enable flags permit and prohibit interrupt corresponding to each interrupt factor. The enable registers of these flags indicate permission if set to "1", prohibition if reset to "0". An individual enable flag is accessed with OUT2/IN2 instructions for which [CN = 0H] has been specified in the operand. The interrupt master enable flag sets interrupt permission and prohibition. On execution of the EI instruction, the master enable flag is set to "1" and interrupt is permitted. On execution of the DI instruction, the master enable flag is reset to "0" and interrupt is prohibited. When an interrupt request permitted by the individual enable flag is issued in the interrupt-enabled state, the CPU receives the interrupt and, by branching to the different vector addresses, executes the interrupt routine. In interrupt reception processing and interrupt return processing, the master enable flag is in the hold state. When all other interrupts are to be prohibited during interrupt processing, therefore, the DI instruction is executed and interrupt is prohibited. The interrupt master flag can be read into a data memory by an IN2 instruction for which [CN = 2H] is specified in the operand.
Y1 LK20 EF1 Y2 EF2 Y4 EF3 Y8 EF4
Individual enable flag: EF1INTR1 pin EF2INTR2 pin / Timer port EF3Serial interface / Timer port / Decreased voltage detection EF48 bit timer counter Y1 K22 IMF Y2 0 Y4 0 Y8 0
"0" Prohibition "1" Enable
Master enable flag
Reset to "0" on acceptance of interrupt or on execution of the DI instruction. Reset to "1" on execution of the RNI or of the EI instruction.
Note: Do not change the setting of the individual enable flag during interrupt processing.
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(2) Interrupt latch The interrupt latch is set to "1" through the issuing of an interrupt request from peripheral hardware. If interrupt is enabled, an interrupt reception request will be sent to the CPU, which will execute the interrupt routine and carry out branching. The data latch is automatically reset to "0" if an interrupt is received at this time. Interrupt latch data can read by the program and the existence or nonexistence of an interrupt request can be determined on an individual basis. An interrupt latch that has been set to "1" by interrupt request can also be reset to "0", and the interrupt request can be canceled or initialized.
Y1 L21 ILR1 Y2 ILR2 Y4 ILR3 Y8 ILR4
Interrupt latch reset Y1 K21 IL1 Y2 IL2 Y4 IL3 Y8 IL4
If set to "1", the interrupt latch is reset to "0".
Interrupt latch data
0: No interrupt 1: Interrupt
Set to "1" on issuance of interrupt request and reset to "0" on interrupt acceptance.
IL1INTR1 pin IL2INTR2 pin IL3Serial interface / Timer port / Detected decrease voltage IL48-bit timer counter
Note: Do not execute interrupt latch reset during interrupt processing. (3) Interrupt priority circuit block The interrupt priority circuit is a circuit that determines the order in which interrupts are processed if interrupt requests occur simultaneously or if interrupt is enabled after multiple interrupt requests have occurred. Vector addresses to the interrupt routine are also generated by this block. The interrupt priority level can be set through programming. The priority level is determined by setting the interrupt ID No. corresponding to each interrupts factor to the interrupt priority level setting port. The interrupt priority level setting ports are composed of priority levels 1 to 4, and the circuit sets the interrupt ID No. in order of the priority levels 1 to 4. For instance, when the interrupt priority level is set in the order of serial interface (2), INTR1 pin (0), INTR2 pin (1) and timer counter (3), then 2h, 0h, 1h, and 3h (L14(6) = 2h, L14(7) = dh) are set to priority levels 1 to 4. These ports can be accessed with an OUT1 instruction for which [CN = 4H] is specified in the operand and 6h and 7h are specified for the data selection ports (K/L1A).
Interrupt ID No. 0 1 2 3 Y1 L14(6) Y2 Y4 Y8
Interrupt Factor INTR1 pin INTR2 pin / timer port Serial interface / timer port / decreased voltage detection Timer counter Y1 L14(7) Y2 Y4 Y8
Vector Address 0001H 0002H 0003H 0004H
PRI1-0 PRI1-1 PRI2-0 PRI2-1
PRI3-0 PRI3-1 PRI4-0 PRI4-1
Priority 1
Priority 2
Priority 3
Priority 4
Interrupt priority setting port
Interrupt ID No. is set.
Note: Do not set the same interrupt ID No. to each interrupt priority level. Note: Do not change the interrupt priority setting during interrupt permission and interrupt processing. Note: Interrupt priority after system reset reverts to an order corresponding to that of the interrupt ID No.'s (i.e., ID No. 0 Priority Level 1).
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(4) Change of interrupt factor From among the ID numbers, ID Nos. 1 and 2 can be used to select, respectively, INTR2 pin / timer port and serial interface / timer port / decreased voltage detection. These changes are made through the control port in each block. Since selection is possible through the following settings, select according to the specification. These settings are also made when routine initialization is being carried out. Do not perform the change while interrupt enable or interrupt processing is in progress. Carry out any change in a state other than these states, and always reset the interrupt latch after the change.
Decreased voltage detection control 2 Detected decrease voltage control 2
Y1 L11(F) Y2 INT LB SEL Y4 Y8
Interrupt factor of interrupt ID No. 2 2 Interruption factor of interruption ID No.
INT LB ENA SEL 0 0 0 1 1 0 1 CK SEL * 0 1 * * Interruptionfunction Interrupt function
SIO Interrupt SIO Interruption 100 Hz Timer Interrupt 100Hz Timer Interruption
200HzHz Timer Interrupt 200 Timer Interruption
Decreased voltage detection interrupt Detected decrease voltage interruption
Y1 L2A
Y2
Y4 CK SEL
Y8 ENA
0 1 1
Prohibition
Timer interrupt control Timer interruptioncontrol
Y1 L22
Y2
Y4
POS2
Y8
NEG2
INTR2 control Interruption factorof interrupt ID No. 1 1 Interrupt factor of interruption ID No. POS2 NEG2 0 0 1 0 1 0 0 0 1 1 CK SEL 0 1 * * * Interruption function Interrupt function
100 Hz Timer Interruption Interrupt 100Hz 200 Hz Timer Interruption 200Hz Timer Interrupt
Rising edge
External interrupt External interruption of INTR2 pin INTR2 pin
Falling edge Both edge Both edges
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2. Interrupt Reception Processing
The interrupt request is held until interruption is received, it interrupts by system reset operation or the program and it resets a latch to "0" through programming. Interrupt reception operation is as shown below. 1) Each item of peripheral hardware outputs each interrupt request and sets the interrupt latch to "1" if the interrupt conditions are fulfilled. 2) If an interrupt enable flag corresponding to a particular interrupt factor or a master enable flag is set to "1", the CPU receives its interrupt, and the corresponding interrupt latch is reset to "0". 3) Any interrupt with a priority level below the accepted interrupt factor is prohibited. 4) The contents of the address stack pointer (ASP) and the interrupt stack pointer (ISP) are adjusted by -1. 5) The contents of the program counter (PC) are evacuated to the address stack register. The contents of the carry flag (Ca), G-register (G-REG), data selection and data register (DATA) are evacuated to the interrupt stack register. At this time, the contents of the program counter change to the next address for the time the interrupt was received or the next address for which interrupt was enabled. 6) The contents of the vector address corresponding to the received interrupt are transferred to the program counter. 7) The contents of the vector address are executed. Steps 2) to 6) are executed in one instruction cycle. This instruction cycle is called an "interrupt cycle".
In the case of an interrupt enable period
Instruction IMF ( Master enable flag ) Interrupt signal Interruption signal
Interrupt signal Interruption signal
EI
instruction
Interrupt Interrupt ion cycle cycle
IL (Interrupt latch) ( Interruptionlatch) 1 instruction cycle Interruptionenable period Interrupt enable period Interruption processing routine Interrupt processing routine Interruption reception Interrupt reception
In the case of an interrupt retention period
Instruction IMF ( Master enable flag ) Interrupt signal Interruption signal
Interrupt signal Interruption signal
EI
instruction
Interrupt Interrupt ion cycle cycle
IL (Interrupt latch) ( Interruption latch) Interruption enable period Interrupt retention period Interruption processing routine Interrupt processing routine Interruption reception Interrupt reception
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3. Return Processing from the Interrupt Processing Routine
The only RNI instruction is used to return the operational state to the processing being carried out before reception of the interrupt from the interrupt routine. Execution of the RNI instruction causes the following processing to be carried out automatically in sequence. 1) 2) Interrupt of the priority below the returning interrupt factor is permitted. The contents of the interrupt stack register specified by the interrupt stack pointer are returned to the G-register, data selection, carry flag, and data register; and the contents of the address stack register data specified by the address stack pointer are returned to the program counter. The contents of the address stack pointer (ASP) and the interrupt stack pointer (ISP) are adjusted by +1.
3)
The RNI instruction for the above-mentioned processing is processed in one instruction cycle. Note: Always execute the return from interrupt using the RNI instruction.
4. Interrupt Processing Routine
If interrupt has been permitted, the CPU accepts the interrupt request regardless of the program executed at that time when the interrupt request is issued. To return to the original program on execution of interrupt processing, therefore, it is necessary to restore the original operational state, as if interrupt processing had not occurred. For this reason, it is necessary to perform shunting and return operations within the interrupt processing routine, at least for those register and data memories that can be operated within the interrupt processing routine. (1) Evacuation processing When the CPU accepts the interrupt, it automatically evacuates the content of G-register, data selection, carry flag and data register to the interrupt stack register. The contents of the area of the data memory and the general register used by the interrupt processing routine are evacuated as necessary by the program before use Return processing The contents of the G-register, data selection, carry flag, and data register return automatically when the RNI instruction is executed. Therefore the return processing works in the opposite way to that of the evacuation processing previously mentioned.
(2)
5. Multiplex Interrupt
Multiplex interrupt is a method of processing other interrupts during interrupt processing. As shown in the figure, the separate interrupt factors C and D are processed during the interrupt processing of interrupt factors A and B. The depth of interrupt at this time is called the interrupt level.
Main routine Interrupt level 1 Interrupt level 2 Interrupt level 3 Interrupt level 4
MAIN
B
D
A
B
C
D
C
Example of multiplex interrupt
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Exercise particular care regarding the following points when using multiplex interrupt: 1) 2) 3) (1) The priority of the interrupt factors Restrictions on the address stack levels used when interrupt requests are issued. Shunting processing for the carry flag, data memory, etc.
Priority of interrupt factor The order of priority for multiplex interrupt becomes A < B < C < D as shown in the figure. When an order of priority of this type applies, the processing of interrupt C must have priority during the interrupt processing of A or B, while the processing of interrupt D is in turn given priority during execution of interrupts C. Multiplex interrupt requires the setting of priority levels. For example, for interrupt factors A and B, let us assume that a request is issued for factor A every 10 ms, with an interrupt processing time of 4 ms; and that a request is issued for factor B every 2 ms, with an interrupt processing time of 1 ms. When there is no order of priority for A and B, then, should an A interrupt request occur during the interrupt processing of B, it may sometimes be the case that the A interrupt processing is executed and the B interrupt processing is not. In such a case, it is necessary to set the order of priority of A < B through programming and prohibit any A interrupt during interrupt processing of B, and also allow a B interrupt to be received even during the interrupt processing of A. Priority ordering of this kind is set through the priority level ports (L14(6), L14(7)), described in the item on the interrupt priority circuit block. Setting interrupt priority in the order of factors A < B < C < D prohibits during the processing of a prioritized interrupt any interrupt with the same priority level or lower. For example, all interrupts are prohibited during factor D interrupt, while during processing of a factor C interrupt, factor D interrupt is enabled while factor A, B and C interrupts are prohibited. Any change in the interrupt order is prohibited during the processing of an interrupt. To prohibit the acceptance of a higher-priority interrupt factor during the execution of a lower-priority interrupt, use a DI/EI instruction to prohibit interrupt in the program area where prohibition is required. Restriction of address stack levels As described in the section on interrupt reception processing, when an interrupt request is issued, the return address is automatically evacuated to the address stack register; and the G-register, data selection, carry flag and data register are automatically evacuated to the interrupt stack register. There are four interrupt stack levels and 16 address stack levels. The content of the interrupt stack register and the address stack register is broken when the interrupt stack levels and the address stack levels are exceeded; it is therefore necessary to use them in such a way to ensure they are not exceeded. Since it can also be used with the execution of a subroutine call command, the address stack register should take into account the address stack levels for both interrupt and subroutine calls. Evacuation processing When using multiplex interrupt, it is necessary to secure the evacuation area for evacuation processing separately for each Interrupt factor.
(2)
(3)
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External Interrupt and Timer Counter Functions
There are two types of pin for external interrupt: INTR1 and INTR2. An interrupt request is issued on detection of the edge of the signal applied to pins INTR1 and INTR2, whether rising, falling or both. The interrupt input pins also combine the functions of I/O port; break during backup; and, in the case of the INTR2 pin, PLL INH input pin. The timer counter is an 8-bit binary counter and has timer mode and pulse width measurement mode functions. In pulse width measurement mode, the pulse width input from the external interrupt pin (INTR1) is measured. This can be used for purposes such as detecting the leader pulse of a remote control.
1. External Interrupt Function
There are two types of pin for external interrupt, INTR1 and INTR2, and an interrupt request is issued on detection of the edge of these inputs. The inputs incorporate a Schmitt circuit and a noise canceller, the frequency of the CPU clock (low-speed oscillation clock: 75 kHz; high-speed oscillation clock: 300 600 kHz) being used for the noise-filtering clock. Any pulse of less than 1 ~ 3 clocks of the CPU clock is removed as noise; and an interrupt is generated when a pulse at or over 1 ~ 3 clocks of the CPU clock (at the time of a 75 kHz oscillation: 13.3 ~ 40 s) is input. Either the rising or the falling edge, or both, can be selected for each pin. The pin used for the external interrupt function also serves as an I/O port. Interrupt will be permitted if edge selection is enabled through use of the external interrupt control port. The external interrupt input state can be read from the I/O port 4 input data port (K33), which is used in combination. The INTR1 pin is used in combination with the input pin of the pulse width measurement mode function of the timer counter. The INTR1 control port is also used to control the logical setting of the pulse. (Refer to the section on the timer counter.) The external interrupt of the INTR2 pin is selected together with the timer port interrupt. When external interrupt of the INTR2 pin is used, it is necessary to set the timer port. (Refer to the sections on the timer port and on changing the interrupt factor.) The program will branch to address 0001H if an INTR1 pin interrupt is received, to address 0002H if an INTR2 pin interrupt is received.
Y1 Y2
NEG1
Y4
POS2
Y8
NEG2
L22
POS1
INTR1 Control
INTR2 Control INTR2 external interruption / Control of timer port interruption POS2 NEG2 0 1 0 1 0 0 1 1 External interrupt of INTR2 pin Interrupt Function 100/200Hz timer interrupt Edge Select I/O port function Rising edge Falling edge Both edges
Control of INTR1 external interruption POS1 NEG1 0 1 0 1 0 0 1 1 External interrupt of INTR1 pin Interrupt Function External interrupt prohibition Edge Select I/O port function Rising edge Falling edge Both edges
Note: The function becomes effective when INH input function and break function are permitted on setting of the external interrupt function. Note: When interrupt is permitted, the I/O port 4 control port becomes invalid and is forced to change to an input port.
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2. Timer Counter Function
The timer counter consists of an 8-bit binary counter, a counter coincidence register, a digital comparator, and a control circuit for controlling these items. The timer counter function has a timer mode and a pulse width measurement mode. The timer mode is a mode for detecting a regular time. The coincidence signal pulse is output and the interrupt request is issued when the timer clock is input to the 8-bit binary counter and is in agreement with the contents of the counter coincidence register. In pulse width measurement mode, measurement of pulse width and detection of pulse width are performed through calculation of the timer counter between "H" or "L" levels input from the INTR1 pin. Pulse width detection can be used to detect the leader pulse of remote controls. For both timer mode and pulse width measurement mode, a timer clock of 25 kHz or 1 kHz can be used. (1) Timer counter register configuration The timer counter register consists of counter data, a coincidence register and a control register.
L2A
Y1 ID0 Y2 ID1 Y4 ID2 Y8 ID3
L2B
Y1 ID4 Y2 ID5 Y4 ID6 Y8 ID7
Timer counter coincidence data
K2A
Y1 ID0 Y2 ID1 Y4 ID2 Y8 ID3
K2B
Y1 ID4 Y2 ID5
A coincidence pulse will be output if the data agrees with the timer counter. Y4 ID6 Y8 ID7
Timer counter data
L 2D (Timer counter control) Y1 CK Y2 PW Y4 CR Disable Y8 CR
Timer counter data is read into data memory as binary data.
Timer counter resetWhenever sets "1", counter is reset. "0" Enable "1" Prohibition
Enable counter reset by coincidence pulse.
"0"Timer mode Selection of timer mode and pulse width measurement mode "1"Pulse width measurement mode "0"25 kHz Selection of timer clock "1"1 kHz
INTR1 control ( L22) POS1 0 1 0 1 NEG1 0 0 1 1
Clock enable logic of INTR1 input signal (Effective only when CR Disable = 0 is set.) Not counted Counted in "H" level Counted in "L" level Always in operation
Reset condition of INTR1 input signal (Effective only when CR Disable = 0 is set.)
Falling edge Rising edge Both edges
Note: This becomes invalid when the settings CR Disable = 1 and PW = 0 apply as above.
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(2) Timer mode Timer mode is a mode for detecting a regular time. Whenever the regular time is detected, an interrupt request is executed and the counter reset. At this time, the control bit is set to 25 kHz or 1 kHz, the PW bit to "0", and the CR bit to "0". At this time, the timer coincidence data is Timer time = IDn (coincidence data) x timer clock cycle This sets the data for required timer interval. IDn 1 (HEX)
25 kHz or 1 kHz Timer clock
Timer data
IDn
00H
01H
02H
03H
ID (N - 1)
IDn
00H
01H
02H
03H
Coincidence pulse Request for interrupt and reset timer counter.
(3)
Pulse width measurement mode Pulse width measurement mode enables the detection and measurement of the "H" or "L" pulse width of the INTR1 input. The control bit at this time is used to select 1 kHz or 25 kHz for the timer clock and set "1" to the PW bit. If the PW bit is set to "1", the INTR1 input becomes the input enable signal of the counter clock and the timer clock is input to the timer counter in the enabled state. Then, if the coincidence data values and counter values match, a timer interrupt is issued. The input logic is used in combination with the external interrupt logic setting (POS1/NEG1 bit).The timer counter is "H" level if the POS1 bit and NEG1 bit are set to "1" and "0" respectively; and "L" level if the POS1 bit and NEG1 bit are set to "0" and "1" respectively. * Pulse width detection The pulse width detection function detects a pulse width equal to or greater than a regular pulse width. This function can be used for detection of the leader pulse of remote controls and data detection. At this time the control bit is set to "0" for the GR Disable bit, and the timer counter is automatically reset on completion of pulse width measurement. With automatic reset, no timer interrupt will be issued when the pulse width is below the set value. Only on input of a pulse equal to or greater than the detection pulse width is a timer interrupt issued and detection enabled. This feature enables the detection of data from remote control devices when used in combination with external interrupts. The detection pulse width at this time is as follows: Detection pulse width = Idn (coincidence data) x the cycle of timer clock Idn 1(HEX)
* Measurement of pulse width When the pulse width is being measured, the CR Disable bit of control bit is set to "1", setting to prohibited status the execution of reset to the timer counter when pulse width measurement is finished. On completion of pulse width measurement, the issuing of the external interrupt is detected, and the pulse width can be measured by referencing the timer counter value. The pulse width at this time is as follows: Pulse width = CTn (timer counter data) x the cycle of timer clock After reading of the timer counter data (CR = "1"), the timer counter is reset and initialized.
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INTR1 input
Timer clock
Timer counter data
01H 02H
03H 00H
01H
02H
03H
ID(n-1)
IDn
ID(n+1) ID(n+2) 00H
Coincidence pulse When the counterInterrupt is issued if counteragreement data is corresponding to the data and coincidence data correspond data, it issues it interrupt.
Counter reset pulse
External interruption pulse External interruption issue
Example of timing of pulse width detection operation in pulse width measurement mode (CR Disable = "0")
INTR1 input
Timer clock
Timer counter data
01H 02H
03H
00H
01H
02H
03H
ID(n-1)
IDn
ID(n+1) ID(n+2)
00H
Coincidence pulse Instruction execution Reading of counter data CR="1" External interruption pulse External interruption issue
Interrupt is issued if counter data and When the counter data is corresponding to the coincidence data it interrupt. agreement data, it issues correspond
Reading of counter data CR="1"
Example of timing of pulse width detection operation in pulse width measurement mode (CR Disable = "1")
Note: The counter is reset whenever the CR bit is set to "1". Execute reset if necessary. Note: The end of measurement can be detected through the concomitant use of external interrupt.
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Internal Interrupts and the Interrupt Function
There are four types of internal interrupt: timer port, timer counter, serial interface, and decreased voltage detection. Of these, three types of interrupt: timer port; serial interface; and decreased voltage detection; can serve a double purpose and act as interrupts for other factors. Select and use the necessary interrupt factor. (Refer to the section on changing the interrupt factor.)
1. Timer Port Interrupt
The timer port interrupt is generated on the rising edge of a 100 Hz or 200 Hz timer. For details, refer to the item on the timer port function.
2. Timer Counter Interrupt
The timer counter interrupt is generated if the timer counter value corresponds to the coincidence register value. For details, refer to the item on the timer counter function.
3.
Serial Interface Interrupt
The serial interface interrupt is generated on the ending of serial interface operation. For details, refer to the item on the serial interface function.
4.
Interrupt for Decreased Voltage Detection
The interrupt for decreased voltage detection is generated on detection of decreased voltage. For details, refer to the item on the decreased voltage detection function.
5.
Interrupt Block Configuration
INT LB SEL ENA Interruption of Serial inter interrupt Serial interface face
External interruption INTR2
Timer port interrupt Interruption of timer port Interruption of Detected Decreased voltage decrease voltage detection interrupt CPU clock Noise canceller Noise canceller Edge detected Edge detected
Selector POS2/ NEG2 Interruption of Timer counter Timer counter interrupt Selector ILR1 Selector POS1/ NEG1 1 EF1 R 2 EF2 R 3 EF3 R 4 EF4 R ILR2 ILR3 ILR4
INTR1
25 kHz 1 kHz
CK
Logic Selector change
POS1/NEG1 CT0CT7
PRI1-1/1 PRI1-2/1 PRI1-3/1 PRI1-4/1
Decoder Priority determination Vector address generate circuit La Vector address Interrupt reception signal Interruption receiving signal IMF R DI instruction
8-bit binary counter 8 bit binary counter + PW
R
PW CR Disable EI instruction PW CR Disable CR
Coincidence pulse
Coincidence register (ID0 ~ ID7)
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Timer port
Equipped with 200 Hz, 100 Hz, 10 Hz and 2 Hz F/F bits, the timer is used for counting of clock operations and of tuning scan mode. Through selection in the timer port for interrupt, interrupts can be generated with a 100 Hz or 200 Hz rising edge.
1. Timer port
Timer interrupt control Timer interruption control Y1 L2A 2H F/F Y2 Timer Y4 CK SEL Y8 ENA
Timer port interrupt selection (refer to the section on the interrupt function) Select of timer interruption (refer to section in interruption function) 0 : Serial interface / Decreased voltage detection function Detected decrease voltage 1 : Timer port Selection interruption timer Select of of interrupt 0 : 100 Hz 1 : 200 Hz The 2 Hz is reset whenever "1"is set. The 2 Hz timer F/F is reset every time "1" is set. The counters for 200 Hz, 100 Hz, and 10 Hz bits, and for The 200 Hz, 100 are reset every time "1" bits are 1 kHz and under, H, 10 and under 1 kHz is set. reset whenever "1" is set. Reset port
Y1 K2A 2H F/F
Y2
Y4
Y8
10H 100H 200Hz
The timer ports are accessed with an OUT2/IN2 instruction for which [CN = AH] has been specified in the operand.
2. Timer port timing
The 2 Hz timer F/F is set with the 2 Hz (500 ms) signal and is reset by setting "1" in the 2 Hz F/F of the reset port. This bit is usually used as a clock counter. The 2 Hz timer F/F can only be reset with the 2 Hz F/F of the reset port; therefore not resetting within a 500 ms cycle will result in count errors and failure to obtain the correct time.
2 Hz F/F output 2 Hz F/F reset execution t < 500 ms 2 Hz clock 500 ms t
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The 10 Hz, 100 Hz and 200 Hz timer is output to 10 Hz, 100 Hz and 200 Hz bits respectively with frequency pulses of 100 ms, 10 ms and 5 ms respectively. The 10 Hz and 100 Hz timers have a duty cycle of 50%. The 200 Hz timer is output at a duty cycle of 60% with a high level of 3 ms and a low level of 2 ms. Counters at 1 kHz or below will be reset whenever the reset port's timer bit is set to "1". 100 Hz or 200 Hz timer can be selected for the interrupt. When timer interrupt is enabled, interrupt is generated on the rising of this pulse. If interrupt is received, a program will branch to 0003H address.
3 ms 200 H 2 ms 100 H 5 ms 10 ms Interruption isis issued on the rising edge of the timer. Interrupt issued by the rising edge of the timer.
10 H 50 ms 100 ms
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Input and Output Ports
A maximum of 45 I/O ports are available for the input/output of control signals. These 45 I/O ports include 36 CMOS I/O ports and 9 N-ch open-drain I/O ports. Up to one exclusive input ports and two exclusive output ports are also available. I/O port 3 can be set to the pull-down or pull-up state, while I/O ports 3, 4, 6 and 8 can be set to backup release (break function). Individual input and output ports also serve as the pins for peripheral equipment. Switch them according to the specifications.
1. I/O Ports, Input-only Ports (IN/IN2) and Output-only Ports (OT1/OT2)
Each of the I/O ports, exclusive input ports and exclusive output ports has the following dual-purpose functions and features.
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I/O port 3 is a CMOS I/O port. Pins P3-0 to P3-2 are also used as the serial interface and pin P3-3 is also used as a pulse counter input pin. These pins can be set to pull-up or pull-down state and to the break function. ( Refer to the sections on Serial interface and Pulse counter.) I/O ports 4 and 5 are CMOS I/O ports. Pins P4-0 and P4-1 are also used as external interrupt input pins. Pin P4-1 is also used as the PLL inhibit input pin. Pin P4-2 is also used as the buzzer output pin. Pins P4-3 and P5-0 to P5-3 are also used as the electronic volume pins. Pins P4-0 to P4-3 can be set to the break function. ( Refer to the sections on External interrupt, Back-up, Buzzer output and Volume.) I/O port 6 is a N-ch open-drain I/O port. Voltage can be applied up to the VDB pin level. This port is also used for the 6-bit A/D converter analog input, and can be set to the break function. ( Refer to the sections on A/D converter.) I/O port 8 is an N-ch open-drain I/O port. Voltage can be applied up to 5.5 V. Pin P8-0 is also used as the doubler voltage detection input pin for the DC-DC converter of VT. Pin P8-1 is also used as the clock output pin for the DC-DC converter of VT. Pins P8-1 to P8-3 are also used as the serial interface. These pins can be set to the break function. ( Refer to the sections on the DC-DC converter of VT and Serial interface.) I/O port 9 consists of the N-ch open-drain pin (P9-0) and the CMOS pins (P9-1 and P9-2). P9-0 is also used as the Tr output pin for LPF. Pin P9-1 is also used as the MUTE output pin. P9-2 is also used as the clock output pin for the DC-DC converter. In addition, pin P9-2 is pulled down to serve as the test mode input pin when pin RESET is at the "L" level. This pin must be in the open state or at the "L" level during test mode input. ( Refer to the sections on MUTE output, DC-DC converter of VT and Phase comparator.) I/O ports 10 to 16 are CMOS I/O ports, and also serve as the LCD driver output pins. Pins P16-2 and P16-3 are also used as high-speed oscillators. ( Refer to the sections on the LCD driver and System clock control circuit.) The exclusive input port is the IN input pin of IFin input combination. The IN input can be switched by the program. The two phase comparator output pins can be used as the exclusive output ports (OT1/OT2). These pins output any of three values; an "H" level that is the VDB pin level, "L" level and High impedance. The I/O circuit of 41 pins at I/O ports 3, 4, 5, 8, 9 and 10 to 16 uses the VLCD (3 V) power supply pin. Voltage can be applied up to 3 V, and a stable output current can be obtained because the output is not heavily reliant on the VDD pin power supply. Pin IN2 of I/O port 6 can accept voltage up to the VDB pin level and pin IN can accept voltage up to the VPLL pin level Note: When setting individual pins as input/output ports, refer to the corresponding sections on the Dual-purpose Function. Note: The "H" level of OT1/OT2 output is the VDB level. All the other CMOS I/O ports output the VDD level. Note: The IN input at the input-only port uses the VPLL power supply. The "H" level is VPLL x 0.8 or higher and the "L" level is VPLL x 0.2 or lower. When the VPLL power supply is turned off with the tuner off, IN input becomes unfixed. The input level for the other pins is VDD x 0.8 or higher at the "H" level and VDD x 0.2 or lower at the "L" level. Note: After a system reset, pin MUTE/P9-1 is set to the MUTE output and all the other input and output pins are set to the I/O port input or high impedance. The MUTE output becomes the "L" level during system reset, and becomes the "H" level after release. Note: When the clock stop instruction is executed, the "L" level is outputted at all the pins that have been set to the I/O port ouput. After the clock stop is released, the previous state is outputted.
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2.
Y1
Control Ports of Input and Output Ports
Y2 Y4 Y8
SEL1 SEL2 SEL4 SEL8
Data select
L12( Data port 1) Y1 -0 (0) (1) (2) (3) (4) (5) (6) (7) * (8) -0 (9) -0 (A) -0 (B) -0 (C) -0 (D) -0 (E) (F) -1 -1 -1 -1 -1 -1 -1 -2 -2 -2 -2 -2 -2 * * L38 -3 L39 -3 L3A -3 L3B -3 L3C -3 L3D * L3E -0 L3F -0 -0 -0 -0 I/O port 9 control I/O port 10 control I/O port 11 control I/O port 12 control I/O port 13 control I/O port 14 control I/O port 15 control -0 -0 -0 -0 -0 -0
OUT3 instruction
IN3 instruction
Y2
-1 -1 -1 -1 -1 -1 -1
Y4
-2 -2 -2 -2 -2 -2 *
Y8
* L30 L31
Y1
Y2
Y4
Y8
K30 K31
Y1
Y2
Y4
Y8
I/O port 9 output data -3 -3 I/O port 10 output data I/O port 11 output data -3 I/O port 12 output data -3 I/O port 13 output data -3 I/O port 14 output data * I/O port 15 output data
-0 L32 L33 L34 L35 L36 -0 L37 -0 -0 -0
-1 -1 -1 -1
-2 -2 -2 -2
-3 K32 K33 K34 K35 K36 -3 -3 -3
-0 -0 -0 -0
-1 -1 -1 -1
-2 -2 -2 -2
-3 -3 -3 -3
I/O port 3 output data I/O port 4 output data I/O port 5 output data I/O port 6 output data
I/O port 3 input data I/O port 4 input data I/O port 5 input data I/O port 6 input data
-1
-2
-3 K37 K38 K39
-0
-1
-2
-3
I/O port 8 output data
I/O port 8 input data -0 -1 -2 I/O port 9 input data -0 -1 -2 IN -3
I/O port 10 input data
-1 -1 -1 -1
-2 -2 -2 -2
-3 K3A -3 K3B -3 K3C -3 K3D K3E -0 -0 -0 -1 -1 -1 -2 -2 -2 -3 -3 -3 I/O port 12 input data I/O port 13 input data I/O port 14 input data -0 -1 0 0 I/O port 15 input data -0 -1 -2 -3 I/O port 16 input data Y1
(UnK25 known)
I/Ocontrol3 I/O port 4 control I/O port 5 control I/O port 16 control
-1
-2
-3 K3F
I/O port 16 output data
Y2 IN2
Y4
Y8
(Un(Unknown) known)
I/O port output data CMOS type I/O port 0 Output pin "L" level 1 Output pin "H" level Nch open drain type I/O port 0 Output pin "L" level 1 Output pin High impedance
I/O control data ( Setting of input and output) 0 Setting of I/O port input 1 Setting of I/O port output I/O port input data 0 Input pin "L" level 1 Input pin "H" level
DO1 control Y1 L24 Y2 Y4 M0 Y8 M1 M1 0 0 1 1 DO control Y1 L25 Y2 Y4 M0 Y8 M1
Setting of DO1 / DO2 output status M0 0 1 0 1 OT output Output status Phase comparator output "L" level output "H" level output High impedance
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I/O port input/output settings are determined at the I/O control data ports. Set the I/O control data port bit corresponding to each port to "0" to program as an input port or set to "1" to program as an output port. Determine the output state of an output port by setting the I/O port output data port. Set the output data bit corresponding to each port to "1" to output the "H" level or set to "0" to output the "L" level. I/O control data and I/O port output data are programmed and controlled at the OUT1 instruction data port-3, the OUT3 instruction. When the IN3 instruction is executed, the pin state is read into the data memory. Note that execution of the IN3 instruction has no influence on the contents of the output latch. OT1/OT2 output is programmed by the contents of the DO control port. ( Refer to the section on Phase comparator.) Note: There is no I/O control port for N-ch open-drain ports (I/O ports 6, 8 and 9-0). To set these ports as input ports, set high impedance by specifying output data to "1". Note: I/O port 1, I/O port 2, ... correspond to pin names P1-0 to P1-3, P2-0 to P2-3, .... Note: The contents of output ports become unfixed after a system reset. It is recommended that the output data be determined before output setting. Note: Data select port increments by 1 automatically when L10 to L15, K10 and K11 on the I/O map are accessed. Note: The state of a pin that has been set to output is read when the IN3 instruction is executed. Note: All the input circuits have the AND structure, which turns the AND gate on only when data reading (IN instruction) is executed. There is little influence on consumption current; even when the input is in the floating condition or has midpoint potential. This enables pull-up at a potential lower than the VDD potential and output at three levels. Pay close attention to setting to the break pin, serial interface or interrupt input, because the consumption current will increase rapidly when the input has midpoint potential.
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3. Break Setting and Pull-up/Pull-down Setting
16 pins of I/O ports 3, 4, 6 and 8 can be set as backup release pins (break pins). If there is a change in the input state of an I/O port that has been set to input, the break pin releases execution of the WAIT or CKSTP instruction and restarts the CPU operation. When the break bit of the MUTE port is "1", the MUTE bit is compulsorily set to "1" when there is a change in the input state. ( Refer to the section on MUTE output.) Each pin of I/O port 3 can be programmed to a pull-down or pull-up state with 50 k (standard) at the pull-up/pull-down control port. Adjust settings at the pull-up/pull-down control ports that corresponds to the pins of I/O port 3.
L/K1A Y1 Y2
SEL1 SEL2
Y4
SEL4
Y8
SEL8
Data select
L14 (Data port 4) L14 Y1 Y2 Y4 Y8
I/O I/O port break enabled BP3 BP4 BP6 BP8
(9) (A)
Break enabled (for each I/O port) (I/O)
0: Prohibition 0 1: Enabled 1
I/O3 I/O port 3 pull-up PU0 PU1 PU2 PU3
I/O port 3 pull-down I/O3
Pull-up/pull-down setting /
PU 0 0 1 PD 0 1 *
Pin state Pull-up/pull-down off /
(B)
PD0
PD1
PD2
PD3
Pull-down Pull-up
Note: BP3, BP4, BP6 and BP8 correspond to I/O ports 3, 4, 6 and 8 respectively. PU0/PD0, PU1/PD1, PU2/PD2 and PU3/PD3 correspond to pins P3-0, P3-1, P3-2 and P3-3 respectively. Note: Break is enabled only when the I/O port is programmed as an input port. The input pin that has been set as a break pin must not be used at the intermediate level. Note: Execution of the wait or clock stop instruction requires reading of the input of the I/O port to be released. Note: When the serial interface function, the pulse counter function or the interruption input is used and break is enabled, the wait or clock stop instruction is released due to change in the input of the pin. This requires input setting at the I/O control port and reading of input of the I/O port before the instruction is executed. Note: I/O port 3 can be set to a pull-up or pull-down state when the serial interface function or the pulse counter function is used.
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Pull-up and pull-down settings can be used to configure the key matrix. The key matrix is configured with usual I/O port output as the output of the key matrix and the I/O port 3 that has been set to pull-down or pull-up as the key input. Setting the key input to break enables restarting depending on the presence or absence of this key input when the CDSTP or WAIT instruction is executed. An example configuration of the key input matrix circuit is shown below.
VDD
P3-3 40 39 38 37 36 P3-2 P3-1 P3-0 P16-3 P16-2 P16-1 P16-0
I/O port 3 I/O3 data loading
Pull-up
Pull-up
When P16-3 and P3-1 keys are pressed P6-3P3-1 P16-3 P3-1
P3-3 P3-2 P3-1 P3-0
Pull-up High impedance
P16-3
P16-2 35 P16-1 34 P16-0 33
Example of key input matrix circuit
Note: After the CKSTP instruction is released by key input, there is a standby time of 100 ms. Pay close attention to this time lag.
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MUTE Output
This is the 1-bit CMOS output port for muting control and also used as P9-1 of the I/O port. The MUTE output can be reversed by the output logic setting or changes in the I/O port.
1. MUTE Port
Y1 L/K28
MUTE
Y2
POL
Y4
Break
Y8
MUTE ENA /0
MUTE output enabled MUTE 0:Prohibition (I/O port setting: P9-1) 0 (I/O P9-1) 1:Enabled (MUTE output) 1 () Control by changes in the input state of the Break break pin 0: BreakMUTEthe break pin 0 The MUTE output does not change when the input state of has changed. 1 BreakMUTE"1" 1: The MUTE bit is set to "1" when the input state of the break pin has changed. MUTE output polarity setting MUTE 0:0Positive logic - The MUTE bit is outputted as is. MUTE 1:1Negative logic - The Mute bit is outputted in a reversed state. MUTE MUTE output setting MUTE 0: MUTE output becomes the "L" level in the positive logic and becomes the 0 MUTE "L" "H" "H" level in the negative logic. 1 MUTE output becomes the "H" level in the positive logic and becomes the 1: MUTE "H" "L" "L" level in the negative logic.
The MUTE output is usually used for muting control. The MUTE output is also used as the I/O port function pin (P9-1). The I/O port and MUTE output pin are switched by the MUTE ENA bit. After a reset, this bit is set to "1" and becomes the MUTE output. Data set to the MUTE bit is outputted to the MUTE output pin using positive or negative logic. By enabling the I/O port break function (refer to the section on the input and output ports) and setting the break bit to "1", the MUTE bit can be set to "1" each time the input of the I/O port is changed. This function promptly activates the muting state and prevents noise from being generated in the linear circuit when the band is switched or the radio is turned off using the I/O port input. POL bit sets up the logic of MUTE output. Set it up according to specifications. This port is accessed by the OUT2/IN2 instruction with [CN = 8H] specified in the operand. Note: During a system reset, the "L" level is outputted as the MUTE output. After the reset is released, the "H" level is outputted. During execution of the clock stop instruction, the output becomes the "L" level. After the instruction is released, the previous state is outputted. Note: When the MUTE is controlled by the break function, the break pin sets the MUTE bit to "1". The state of the MUTE bit can be checked at the MUTE bit (K28). The state of the MUTE pin can be checked at the P9-1, I/O port 9 input data port (K38) . Note: When the MUTE bit is set to "1", the electronic volume can be set to -dB. ( Refer to the section on Electronic volume.)
2. Circuit Composition of MUTE Output
MUTE MUTE bit S
POL bit POL
56
MUTE/P9-1
CKSTP CKSTP instruction Break Break bit Break Break pin input change signal
Reset signal
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Serial Interface
This is the 2-channel, 1-system serial interface, which has three functions; a three-wire serial interface, two-wire serial interface and full-duplex UART functions. The serial interface communicates with the extended LSI and microcomputer using CMOS serial interface pins SCK1/TX1 (P3-0), SDIO1 (P3-1) and SI1 (P3-2) or N-ch open-drain pins SCK2/TX2 (P8-2), SDIO2 (P8-3) and SI2 (P8-1) (that can accept voltage up to 5.5V). When the serial interface operation is finished, an interruption is issued. The serial interface consists of the 4-bit input/output serial counter, the 12-bit serial output latch, the 12-bit serial input latch and the control circuit that controls them. The basic operations of the serial interface are as follows. For the serial output, the serial data output bit data is outputted as specified by the serial output counter, and the serial counter is moved up or down by the serial clock so that the data is outputted to the serial output pin in the specified order. For the serial input, serial input data is sequentially taken to the serial latch specified by the serial input counter as in the case of the serial input.
1. Control Port and Data Port for Serial Interface
The serial interface executes control and data transmission and receiving using the control port and data port. These ports are assigned in I/O map data port 2 and accessed by the OUT1/IN1 instruction.
Serial interface control 1 1 2 4 8
Selection of serial interface pin
PSEL * 0 SIO 0 1 Serial interface pin
Each pin for I/O port operation I/O I/O port 3 (CMOS) I/O3(CMOS)
L11(7)
M0
M1
PSEL
SIO
Mode setting
1
I/O8(Nch) I/O port 8 (N-ch open-drain)
Serial interface mode setting
M1 0 0 1 1 M0 0 1 0 1 Serial interface mode
Operation stop
2 2-wired interface 3 3-wired interface UART
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Serial interface control 2 1 2 4 8
L11(8)
CK0
CK1
OSC0
OSC1
Clock setting
Serial clock (transmission rate) frequency setting ()
OSC1 OSC0
Oscillator setting
CK1 0
CK0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
2/3-wired interface clock 2/3 frequency (fSCK) (fSCK)
UART transmission rate (fSCK) UART(fSCK)
fosc/2 fosc/4 fosc/8 fosc/16 fosc/2 fosc/4 fosc/8 fosc/16 fosc/2 fosc/4 fosc/8 fosc/16 fosc/2 fosc/4 fosc/8 fosc/16
37.5kHz 18.75kHz 9.375kHz 4.6875kHz 150kHz 75kHz 37.5kHz 18.75kHz 225kHz 112.5kHz 56.25kHz 28.125kHz 300kHz 150kHz 75kHz 37.5kHz fosc/8bps fosc/32bps fosc/64bps fosc/16bps fosc/32bps fosc/128bps fosc/256bps fosc/24bps fosc/48bps fosc/192bps fosc/384bps fosc/32bps fosc/64bps fosc/256bps fosc/512bps
9375bps 2344bps 1172bps 9600bps mode 2400bps mode 1200bps mode
mode 9600bps
0
0
Low-speed oscillator (75kHz) (75kHz)
0 1 1 0
mode 18750bps 19200bps
0
1
oscillator (300kHz)
High-speed
0 1 1 0
9375bps 2344bps 1172bps
2400bps mode 1200bps mode 9600bps mode
mode 2400bps
18750bps 19200bps mode 9375bps 2344bps 1172bps
1
0
oscillator (450kHz) (450kHz)
High-speed
0 1 1 0
1200bps mode 9600bps mode
mode 2400bps
mode 18750bps 19200bps
1
1
oscillator (600kHz) (600kHz)
High-speed
0 1 1
9375bps 2344bps 1172bps
1200bps mode
1 2 4 8 L11(9)
MASTER POL NchS SIS
Serial interface control 3
0: Select SDIO input pin Selection of SI SDIO SDIO serial input of SDIO 1: Select SI input pin and SI pins SI Selection of I/Ooutput form of serial I/O port pin Selection of serial clock logic for serial data 0: ("" SCK ) Positive logic output ("L" level outputs SCK clock) 1: ("H" SCK SCK clock) Negative logic output ("H" level outputs ) 0: Select CMOS output form CMOS 1: Select N-ch open-drain output form Nch
() Selection of external or internal SCK 0: External clock input (slave) () 1: Internal clock output (master) SCK
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1 2 4 8 L11(A)
STPS SWENA MSB SOS
Serial interface control 4
input setting 0: Pin SDIOSDIO Output setting for serial SDIO output setting 1: Pin SDIOSDIO output of pin SDIO
0: Input/output serial data from the least significant bit Selection of order of serial 1: Input/output serial data from the most significant bit data bits
Serial wait enable setting
0: Prohibition 1: Enabled
Note: SOFSCK When the serial wait is set to be enabled, the SCK output is compulsorily outputted at"L" SOF is outputted. the "L" level and becomes the clock wait state when the serial data (This is effective only in the 2-wired serial mode.)

0: Select the input clock counter Selection of serial clock counter 1: Select the output clock counter stop condition

Serial interface control 7
L11(D)
TSTA1 TSTA2
STP
F/F Reset
"the internal flag each time "1" is set Internal flag reset Resets " " " Serial operation stop Stops serial operation by setting "1" " operation by setting "1" Execute restart in 2-wired mode Restarts " " " Start serial operation in master mode Starts operation by setting "1"
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L11(4)
SO0
L11(5)
SO2
L11(6)
SO6
SO1
SO3
SO4
SO5
SO7
SO8
SO9
SOE
SOF
Serial output data
Data that has been set outputs the output data corresponding to the output counter number to the serial output pin.
0: " " Serial output "L" 1: " " Serial output "L"
K11(4)
SI0
K11(5)
SI2
K11(6)
SI6
SI1
SI3
SI4
SI5
SI7
SI8
SI9
SIE
SIF
Serial input data
" " The state of the serial input pin is inputted to the input data Serial input "L" 0: corresponding to the input counter number at the edge of " " 1: Serial input "H" the shift clock.
1 2 4 8 L11(B)
STA0 STA1 STA2 STA3
Serial interface control 5
Serial counter start data
The specified counter number is set to the serial counter when the serial operation starts.
1 2 4 8 L11(C)
STP0 STP1 STP2 STP3
Serial interface control 6
Serial counter start/stop setting
Serial counter stop data
The serial counter is stopped at the specified counter number.
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Serial interface monitor 1
1 2 4 8 0: stop state 2-wired 2-wired mode: Detection of 1: 2-wired operating Serial operation monitor 2
state UART setting: Detection of 0: Receiving operation receiving (RX) operation UART(RX) stop state state 1: Receiving operation operating state 0: No receiving operation flag Serial receiving execution of receiving operation 1: Execution 2-wired operation state
K11(7)
BUSY1 SOERR RX F/F BUSY2
Serial data output abnormality 0: detection flag 1:
Output data normal Output data abnormal
Serial operation monitor 1
stop state 0: Serial operating state 1: Serial
Serial interface monitor 2
1 2 4 8
OCT0 OCT1 OCT2 OCT3
K11(8)
Serial output counter monitor
The current serial output data number is read.
Serial interface monitor 3 1 2 4 8
Serial counter operation monitor
K11(9)
ICT0
ICT1
ICT2
ICT3
Serial input counter monitor
The current serial input data number is read.
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1-1. Serial Interface Setting and Control Bits
(1) Serial pin setting (PSEL and SIO bits) I/O ports 3 or 8 can be used as serial input/output pins. I/O port 3 has a CMOS structure and I/O port 8 has an N-ch open drain structure. Since voltage up to 5.5V can be applied to I/O port 8, it can do an interface with LSI of 5 V system easily. I/O port 3 is usually used for communication with LSI that drives the VDD power supply in the same power supply system. This port can also be used as a N-ch open-drain port, and accept voltage up to the power supply of the VLCD pin (3 V). Therefore, it can be used as an interface with LSI in power supply systems of 3 V or below. Set this control bit to "0" when the serial interface is not used.
SIO 0 1 1 PSEL * 0 1 Serial interface pin Each pin I/O Port operation I/O port3 I/O port8 Pin structure CMOS Nch open drain Pin type CMOS or Nch open drain Nch open drain Maximum applicable voltage ~VLCD (3 V) ~5.5 V
Note: (2)
These bits are reset to "0" after a system reset.
Type of serial operation (M0 and M1 bits) The serial operation can be selected from three serial interface modes; 3-wired type, 2-wired type and UART. Set this control bit to "0" when the serial interface is not used. When a mode is selected, the pins are switched to the function pins as listed below.
Name of pin being used
M1 0 0 1 1
M0 0 1 0 1
Serial interface mode
Operation stop
I/O3 Select I/O port 3 P3-0 SCK1 SCK1 RX1 P3-1 SDIO1 SDIO1 TX1 P3-2 P3-2 SI1(P3-2) P3-2 P8-1 P8-1 SI2(P8-1) P8-1
I/O8 Select I/O port 8 P8-2 SCK2 SCK2 RX2 P8-3 SDIO2 SDIO2 TX2
2 2-wired interface 3 3-wired interface UART
Note: (3)
These bits are reset to "0" after system reset.
Selection of serial operation clock (CK0, CK1, OSC0 and OSC1 bits) The serial operation clock sets the serial interface operating speed. When the 2- or 3-wired master mode is selected, operation speed can be selected from four types, fosc/2, fosc/4, fosc/8 and fosc/16. When UART is selected, operation speed can be selected from three types, 9600/2400/1200 bps. When a high-speed oscillator is used, the operation speed of the 2- or 3-wired type can be accelerable to 300 kHz, which enables the use of the UART transmission rate, 19200 bps. Refer to the following table and select the operation clock. When the 2- or 3-wired slave mode is selected, these bits revert to "don't care" state, which enables serial clock operation at an operation speed of up to 200 kHz. Note: Note: Note: Note: The duty of the 2- or 3-wired mode is always 50%. When the high-speed oscillator is prohibited, the OSC0 and OSC1 bits revert to "don't care" state. Set all of these bits to "0" when the 2- or 3-wired slave mode is selected. These bits are reset to "0" after a system reset.
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Serial clock (transmission rate) frequency setting ()
OSC1 OSC0 setting
Oscillator
CK1 0
CK0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
2- or 2/3 clock 3-wired interface frequency (fSCK) (fSCK)
UART transmission rate (fSCK) UART(fSCK)
fosc/2 fosc/4 fosc/8 fosc/16 fosc/2 fosc/4 fosc/8 fosc/16 fosc/2 fosc/4 fosc/8 fosc/16 fosc/2 fosc/4 fosc/8 fosc/16
37.5kHz 18.75kHz 9.375kHz 4.6875kHz 150kHz 75kHz 37.5kHz 18.75kHz 225kHz 112.5kHz 56.25kHz 28.125kHz 300kHz 150kHz 75kHz 37.5kHz fosc/8bps fosc/32bps fosc/64bps fosc/16bps fosc/32bps fosc/128bps fosc/256bps fosc/24bps fosc/48bps fosc/192bps fosc/384bps fosc/32bps fosc/64bps fosc/256bps fosc/512bps
9375bps 2344bps 1172bps
mode 9600bps
0
0
oscillator (75kHz) (75kHz)
Low-speed
0 1 1 0
2400bps mode 1200bps mode 9600bps mode 2400bps mode 1200bps mode
mode 9600bps
mode 18750bps 19200bps
0
1
High-speed oscillator (300kHz)
0 1 1 0
9375bps 2344bps 1172bps
mode 18750bps 19200bps
1
0
oscillator (450kHz) (450kHz)
High-speed
0 1 1 0
9375bps 2344bps 1172bps
2400bps mode
mode 1200bps
18750bps 19200bps mode 9375bps 2344bps 1172bps 9600bps mode
mode 2400bps mode 1200bps
1
1
oscillator (600kHz) (600kHz)
High-speed
0 1 1
2- or 3-wired mode Serial clock (SCK) (SCK)
2/3
fSCK
UART mode
UART
tSCK
UART(TX/RX) UART input/output (TX/RX)
(SDIO) Serial input/output (SDIO)
(4)
Serial operation condition setting MASTER bit (Selection of external/internal SCK clock) Set the master or slave mode. Select the internal clock for the serial clock (SCK) to set the serial operation to master mode, and select the external clock to set the serial operation to slave mode. If the master setting is selected, the serial operation will start and the serial clock will be outputted when start setting is made by the serial start bits (TSTA1 and TSTA2 bits), and the operation will stop under the serial counter stop condition. The serial clock selected by the clock selection bits (CK0, CK1 bit) will be outputted. If the slave setting is selected, the serial operation will start automatically when the external clock is inputted. For the 2- or 3-wired type, frequencies no higher than 200 kHz (fSCK) can be inputted as the external clock.
0: External clock input (slave) Selection of external or internal SCK clock (MASTER bit) 1: Internal clock output (master)
Note: Note:
Select the slave setting when the UART is selected. This bit is reset to "0" after a system reset.
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POL bit (Selection of serial clock logic for serial data) Select the logic for shift clock input/output of the serial clock. When "1" is set to the bit of POL and a master setup is selected, serial operation stops on the "H" level in the state of a stop, if operation starts, the serial clock outputs and it stops on "H" level. When the POL bit is set to "0", the logic will be reversed, that is, the operation will start from the "L" level. Together with the output logic, this bit controls the serial counter operation edge by the serial clock input/output and the serial input take-in edge. The timing operation by the POL bit is as shown below.
0: Positive logic output (SCK clock is outputted from the "L" level) 1: Negative logic (SCK clock is outputted from the "H" level)
Selection of serial clock logic for serial data (POL bit)
(A) 2-wired master and slave and 3-wired slave modes (POL="1") A POL="1" Take in data input
(A) 2-wired master and slave and 3-wired slave modes (POL="1") B POL="0" Take in data input
Serial clock
Serial output Serial output counter (OTC0 to 3 bit) OTC0 3 Serial input Serial input counter (ITC0 3 ITC0to 3 bit)
Serial clock
Serial output Serial output counter (OTC0 3 OTC0to 3 bit)
Serial input
Serial input counter (ITC0 3 ITC0to 3 bit)
(C) 3-wired master mode (POL="1") C POL="1"
(D) POL="0" D 3-wired master mode (POL="0")
tsck/4 Serial clock
Serial output Serial output counter (OTC0 to 3 bit) OTC0 3
tsck/4
tsck
tsck/4
Serial clock Serial output Serial output counter (OTC0 to 3 bit) OTC0 3 Serial input Serial input counter (ITC0 to 3 bit) ITC0 3
tsck/4
tsck
Serial input
Serial input counter (ITC0 to 3 bit) ITC0 3
Note: Note:
When the 3-wired master mode is selected, the serial output (serial output counter) changes in timing shifted by tsck/4. When the 2-wired master mode is selected, the serial clock is operated by the input of the SCK pin clock. Therefore, the serial operation will not start if the SCK pin clock does not output waveforms for some reason. Set to POL = "0" when UART is selected. This bit is reset to "0" after a system reset.
Note: Note:
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NchS bit (Selection of output form for the serial I/O port pins) Set the serial interface input/output circuit type. Setting this bit to "0" to select the CMOS circuit form, and setting this bit to "1" to select the N-ch open-drain circuit. 0: Select the CMOS output form Selection of output form for serial I/O port pins (NchS bit) 1: Select the N-ch open-drain output form
NchS 0 1
I/O port 3 I/O port 8 I/O3 I/O8 CMOS type Setting disabled CMOS N-ch open-drain type Nch
Note: Note: Note:
Select the N-ch open-drain setting when the 2-wired mode is selected. This bit is also effective when the UART is selected. This bit is reset to "0" after a system reset.
SIS bit (Selection of SDIO pin or SI pin for serial input) Select a serial input pin. Set this bit to "0" to select the SDIO pin for serial input. Set this bit to "1" to select the SI pin for serial input. The I/O port function is enabled for the SI pin. Therefore, when the SI input pin is used for serial input, it is necessary to set the I/O port corresponding to this pin as an input port. When the SDIO pin is used for serial input, the SI pin can be used as an I/O port. 0: Select the SDIO input pin 1: Select the SI input pin
Selection of SDIO or SI pins for serial input (SIS bit)
Note: Note: Note: Note:
When the SI pin is selected, set the I/O port corresponding to this pin as an input port. When the SDIO input is selected, the SI pin can be used as a normal I/O port. Select the SDIO input when UART is selected. This bit is reset to "0" after a system reset.
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STPS bit (Selection of the serial clock counter stop condition) The serial operation stops when it becomes the stop position of a serial counter. There are two types of serial counters, the serial output counter and the serial input counter. The stop condition is switched between the output and input counters. 0: Select the input clock counter 1: Select the output clock counter
Selection of serial clock counter stop condition (STPS bit)
(A) 2- or 3-wired mode (POL="0", STP="0") A POL="0" STP="0" Stop Serial clock SCK) (SCK)
(B) B POL="0" STP="1" 2- or 3-wired mode (POL="0", STP="1") Stop Serial clock SCK) (SCK) Serial output counter (OTC0 3 OTC0 to 3 bit) Serial input counter (ITC0 3 ITC0 to 3 bit)
Serial output counter (OTC0 3 OTC0to 3 bit) Serial input counter (ITC0 3 ITC0to 3 bit)
(C) 2- or 3-wired mode POL="1" STP="0" C (POL="1", STP="0")
(D) 2- or 3-wired mode (POL="1", STP="1") D POL="1" STP="1"
Stop
Serial clock (SCK) SCK) Serial clock SCK) (SCK) Serial output counter (OTC0 to 3 bit) OTC0 3 Serial input counter (ITC0 to 3 bit) ITC0 3
Stop
Serial output counter (OTC0 to 3 bit) OTC0 3 Serial input counter (ITC0 to 3 bit) ITC0 3
Note: Note:
Set to STPS = "1" (Select the clock output counter) as shown in (B) when the 2-wired or UART mode is selected. This bit is reset to "0" after a system reset.
SWENA bit (Serial wait enable) This control bit is effective only when the 2-wired mode is selected. usually, set this bit to "1" when the 2-wired mode is selected. If serial wait is enabled in the 2-wired mode, the SCK is outputted at the "L" level and becomes the clock wait state and the serial clock is suspended when the serial output counter (OCT0~3) becomes "F" (HEX).
0: Prohibition
Serial wait enabling setting (SWENA bit)
1: Enabled (Set to "1" when the 2-wired setting is selected)
When the 2-wired mode is selected (POL="1", STP="0", SWENA="1") POL="1" STP="0" SWENA="1"
Serial clock SCK) (SCK) Serial output counter (OTC0 3 OTC0to 3 bit)
SCK"L" SCK is outputted at the "L" level and is suspended F(HEX)
Note: Note:
Set to SWENA = "0" when the 3-wired or UART mode is selected. This bit is reset to "0" after system reset.
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SOS bit (Output setting for SDIO pin serial output) This control bit switches the serial data input/output pin (SDIO pin) between data output and input. Set this bit to "0" for serial data input or set to "1" for serial data output. In the 3-wired mode, switching between input and output is executed when the instruction to this bit is executed. In the 2-wired mode, switching between input and output is updated and determined under the following conditions after this bit is specified. Output setting for SDIO pin serial output (SOS bit) 0: SDIO pin input setting 1: SDIO pin output setting
Update timing of SDIO pin input/output switching in the 2-wired mode Stop condition Falling edge of the shift clock when the communication is started Falling edge of the serial clock after ACK input/output
SDIO input/output switching timing in the 2-wired mode (mastermode) SDIO
Serial clock (SCK) SCK) Serial input/output (SDIO) SDIO) Execution of instruction
TSTA1="1" TSTA1="1" execution SOS SOS bit setting
ACK
TSTA2="1" execution TSTA2="1"
SOS SOS bit setting SOS SOS bit setting
ACK
STP="1" execution STP="1"
SDIO input/output update timing SDIO
SDIO SDIO input/output update timing
SDIOSDIO input/output update timing
SDIO input/output switching timing in the 2-wired SDIO mode (slave mode) Serial clock (SCK) SCK) Serial input/output (SDIO) SDIO) Execution of instruction
ACK
ACK
SOS SOS bit setting
SOS SOS bit setting
SOS SOS bit setting
SDIO SDIO input/output update timing
SDIO SDIO input/output update timing
SDIO SDIO input/output update timing
SDIO input/output switching timing in the 3-wired mode SDIO
Serial clock SCK) (SCK) Serial input/output SDIO) (SDIO) Execution of instruction
Input
Output
Input
0 SOS="1"
1 SOS="0"
0 SOS="1"
Note: Note: Note:
If the SOS bit is set in the 3-wired mode, the input/output of the SDIO pin will be updated when the instruction is executed. Always set the SOS bit to "1" when UART is selected. This bit is reset to "0" after a system reset.
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MSB bit (Selection of the order of serial data bits) This control bit controls the arrangement of serial data input/output data. Select whether data input/output started from the most or the least significant bit respectively. For the serial interface, serial data specified by the serial counter is inputted and outputted. The MSB bit controls the serial counter to count up or down. When the MSB bit is set to "0", the serial counter counts up. When the MSB bit is set to "1", the serial counter counts down.
Selection of the order of serial data bits (MSB bit) 0: Input/output serial data beginning with the least significant bit 1: Input/output serial data beginning with the most significant bit
Serial counter and serial input/output timing (when MSB= POL="0" MSB="0""0" and POL= "0")
Serial clock (SCK) SCK)
Serial output counter (OTC0 OTC3) OTC0to OTC3) counter (ITC0 to ITC3) ITC0 ITC3) Serial input/output SDIO) (SDIO)
Serial input

SOE
SOF
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
SO8
SO9
()HEX (Note) Shown in HEX notation
Serial counter and serial input/output timing (when MSB= POL="1" MSB="1""1" and POL= "1")
Serial clock (SCK) SCK) Serial output counter (OTC0 OTC3) OTC0to OTC3) counter (ITC0 to ITC3) ITC0 ITC3) Serial input/output (SDIO) SDIO)
Serial input

SO9
SO8
SO7
SO6
SO5
SO4
SO3
SO2
SO1
SO0
SOF
SOE
(Note) Shown ()HEX in HEX notation
Note:
Serial data corresponding to the serial output counter is outputted to the serial output pin. The state of the serial input pin corresponding to the serial input counter is stored in the serial input data at the edge. Input and output serial counters have up and down edges reverse to each other. If any serial input/output data not present in the serial counter is designated, the output will be "L" and the input will be "don't care". This bit is reset to "0" after a system reset.
Note: Note: Note:
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Serial counter, Serial data (STA0 to 3, STP0 to 3, OCT0 to 3 and ICT0 to 3 bits, SO0 to SO9/SOE/SOF, SI0~SI9/SIE/SIF) The serial counter consists of the serial input counter (ICT0 to 3) that counts the serial input clock and the serial output counter (OCT0 to 3) that counts the serial output clock. When stop is executed (STP = "1"), these serial counters are preset to the stop data (STP0 to 3). When start is executed (TSTA1 = "1", TSTA2 = "1") or the external serial clock is started, these serial counters are preset to serial counter start data (STA0 to 3) and counted by the serial clock. When the serial counter coincides with the serial stop data (STP0 to 3), the serial counter is stopped and an interruption is issued. The operating state can be checked on the serial counter monitor (ICT0 to 3, OCT0 to 3). Serial counter start data (STA0 to 3 bits) When the serial operation is started, the start data is set to the serial counter. Serial counter stop data (STP0 to 3 bits) When a stop is executed (STP = "1"), the stop data is set to the serial counter. After the serial counter operation, the serial operation is stopped in the stop data position, and an interruption issued. Operation monitor for serial output counter (OCT0 to 3 bits) The operating state of the serial output counter can be detected. Operation monitor for serial input counter (ICT0 to 3 bits) The operating state of the serial input counter can be detected. Serial data consists of 12 bits each of serial output data (SO0 to SO9/SOE/SOF) and serial input data (SI0 to SI9/SIE/SIF). For serial output data, the serial data corresponding to the serial output counter number is outputted to the serial output pin. For serial input data, the state of the serial data input pin is read at the edge of the serial clock corresponding to the serial input counter number. When the 2-wire mode is selected, the SOE/SOF bits in the serial output data are automatically set to "1" when the serial operation is started or when stop is executed (STP = "1") with the master setting. usually, the bits of SO0/SI1 to SO7/SI7 are used for serial input/output data. The SOE bit is used as the output bit of the serial stop state,while the SOF/SIF bits are used as input/output data of ACK. When UART is selected, the bits of SO0/SI1 to SO7/SI7 are used for UART input/output data, while the SO8/SI8 bits are used as parity bits. The SO9 bit is used for the output of the stop output data. When the 3-wire mode is selected, up to 14 bits of serial data can be inputted and outputted. Set the serial data start and stop data according to the number of bits, and specify this number.
Example of serial operation timing when the 3-wire mode is selected (when MSB="0" POL="0" STPS="1"MSB= "0", POL= "0" and STPS= "1")
STP0 3="0"
Serial clock (SCK) SCK)
STA0 3="7"
Stop when the serial counters match.
Serial output counter (OTC0 toOTC3) OTC0 OTC3) counter (ITC0 to ITC3) ITC0 ITC3)
Serial input/output (SDIO) Serial input

SO0
SO7
TSTA1= "1" execution TSTA1="1"
SO6
SO1
SO1
SO0
SO7
SO6
SO1
SO0
SDIO)
Execution of
TSTA1= "1" execution TSTA1="1"
Issue of interruption Issue of interruption
instruction STP="1"
STP= "1" execution
(Note) Shown in HEX notation ()HEX
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(5) Start and stoppage of serial operation TSTA1 and TATA2 bits (Start of serial operation) The TSTA1 bit controls the start of serial operation in the master mode. When this bit is set to "1", the serial clock will be outputted and the serial interface operation will start. When start is executed in the 3-wire mode, the serial counter start data (STA0 to 3) will be preset in the serial input/output counters, and serial output data corresponding to the start data will be outputted. After that, serial data (SO0 to SO9, SOE, SOF) will be outputted sequentially according to the serial clock (SCK). When start is executed in the 2-wire mode, the start condition pulse will be outputted to the serial data output. When this start condition is satisfied, the serial operation will be started. When start is executed in the UART mode, the start pulse will be outputted from the TX pin, and then the same operation as in the 3-wire mode will be executed. In slave mode, operation can be started by the external serial clock without the need to use this control bit. The TSTA2 bit controls the restart of serial operation in the 2-wire master mode. When start is executed by the TSTA1 bit, the start condition will be outputted, the 8-bit serial clock will be active and the operation will enter the serial wait state. When the TSAT2 bit is set to "1", the serial operation will be restarted for serial input/output. Start of serial operation in the master mode (TSTA1 bit) When this bit is set to "1" in the master mode, serial operation will start. When in 2-wire mode, the start condition will be outputted automatically. When in UART mode, the start pulse will be outputted. Execution of restart in the 2-wire mode (TSTA2 bit) When this bit is set to "1", the operation will be restarted.
Note: Note:
When these bits are set to "0", the system will be in a "don't care" state. Allow the wait time that corresonds to at least one cycle of the serial operation clock between execution of stop (STP = "1") and execution of start (TSTA = "1").
STP bit (Stoppage of serial operation) The STP bit controls the compulsive stoppage of serial operation, the initialization of internal state and the output of the stop condition. When the STP bit is set to "1" (stop is executed), the serial counter stop data (STP0 to 3) is preset to the serial counter and initializes the internal state. When a stop is executed during serial operation in master mode, the serial clock operation will be stopped. When a stop is executed in the master 2-wire mode, the stop condition will be automatically outputted from the serial data output and the serial clock in addition to the operation as mentioned above. Stoppage and initialization of serial operation in the master mode (STP bit) When this bit is set to "1", the operation will be stopped and initialized. In the 2-wire mode, the stop condition will be outputted automatically. Note: Note: When this bit is set to "0", the system will be in a "don't care" state. After setting the condition, be sure to execute stoppage (STP = "1") for internal initialization.
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(6) Serial operation monitor BUSY1/BUSY2 bits (Operation monitor) The BUSY1/BUSY2 bits detect the serial operating state. The BUSY1 bit can detect the serial clock operating state, while the BUSY2 bit can detect the operating state in the 2-wire mode or the receiving operation state in the UART mode. When interruption is enabled, it will be issued at the falling edge of the BUSY1 bit and the program will branch to address 0001H. SOERR bit (2-wire serial output error flag) The SOERR bit is used to detect arbitration in the 2-wire multi master mode. When serial data is outputted in the master mode, the output state is compared to the internal output data. If there is any discrepancy between them, the serial operation will be stopped automatically and the SOERR bit set to "1". When this state is detected, the serial clock and data respectively will be opened and the operation will continue. For normal arbitration detection, the serial operation will be stopped by the clock supplied from another master. When the 2-wire operation is completed, FF Reset = "1" will be set and the flag will be reset. This detection is carried out during serial output setting, regardless of the master or slave mode. Therefore, program processing is required if any discrepancy occurs in the output data due to noise or for any other reason. Usually, provide a timer to detect this bit if there is no issue involving interruption or the BUSY1 signal does revert to "L" after a certain time has elapsed. If the detected bit is "1", set the STP bit to "1" to execute stop and initialization. In any other modes than the 2-wire mode, this bit is in the "don't care" state.
In the 2-wire mode, the serial clock and the serial output pin are opened.
Serial clock SCK) (SCK)
Serial input/output (SDIO) SDIO)
Serial data error SOERR SOERR bit
RX F/F bit (Receiving flag) The RX F/F bit detects the receiving of UART or the 3-wire slave. This bit is effective only in slave mode. When the serial clock receives input or UART when in slave mode, this bit is set to "1". After receiving is completed, refer to the received serial data. This bit is reset to "0" by setting the FF Reset bit to "1". F/F Reset bit (Internal flag reset) This bit initializes the internal flag. Each time this bit is set to "1", the internal flag will be reset. Serial receiving execution flag (RX F/F), the serial data output error detection flag in the 2-wire mode, and the serial wait are reset and released. In the 2-wire mode, the system will enter the wait state after output of the serial output data SOF bit. Usually, the SOF/SIF bits are used as the acknowledgement of (ACK) bits. After reading the ACK bit input/output, serial operation will be restarted by execution of the F/F Reset bit. Internal flag reset (F/F Reset bit) "The internal flag is reset each time this flag is set to "1". The wait state is released in the 2-wire mode. Start and stop operation timing
Stop condition Start condition
in the 2-wire mode
Stop condition
Serial clock (SCK)
SCK)
Serial input/output (SDIO) SDIO) Execution of instruction
STP= "1" execution TSTA= "1" execution STP="1" TSTA1="1"
ACK
TSTA2= "1" execution TSTA2="1"
ACK
STP= "1" execution STP="1" F/F Reset= "1" F/F Reset="1"execution
Serial output counter (OTC0 to OTC3) OTC0 OTC3)
Serial input counter (ITC0 to ITC3)
F/F Reset="1" F/F Reset= "1" execution
E
F
F
E
E

F

F
E
ITC0 ITC3)
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1-2. Examples of Serial Mode Settings
Examples of settings in the 3-wire, 2-wire and UART modes are shown below. Adjust settings according to the required specifications. (1) Example of 3-wire serial mode setting
Setting bit M0, M1 CK0, CK1, OSC0, OSC1 MASTER POL NchS SIS STPS SWENA MSB SOS STA0~3 STP0~3 PSEL, SIO 3-wire setting (M0 = 0, M1 = 1) Serial clock frequency setting Master setting (MASTER = 1): Refer to an example of master operation timing. Slave setting (MASTER = 0): Refer to an example of slave operation timing. Serial clock stop state = L Data output at the rising edge and data input at the falling edge (POL = 0) CMOS setting (NchS = 0) Setting of SDIO pin to serial input (SIS = 0) Setting of stop condition to input counter (STPS = 0) Stop weight disabled (SWENA = 0) Output beginning with the least significant bit (MSB = 0) Data output: SOS = 1, Data input: SOS = 0 Serial input/output start data: 0h Serial input/output stop data: 8h Select CMOS pin (SDIO1, SCK1) (PSEL = 0, SIO = 1) Condition setting data
*
Example of serial interface timing in the 3-wire master mode
2 3 8 2 8
Serial clock (SCK1) outputSCK1)
Serial input/output SDIO1) (SDIO1)
Serial output counter OTC0 to OTC3) (OTC0 OTC3)
SO8
SO0
SO1
Data output
SO2
SO7
HZ
SI0
SI1
Data input
SI7
HZ
SO7

TSTA= "1" TSTA1="1" execution
SOS="0" SOS= "0" setting
TSTA1= "1" TSTA1="1" execution
Serial clock stop
Execution of instruction STP="1" STP= "1" execution
BUSY1
Issue of interruption
*
Example of serial interface timing in the 3-wire slave mode
Serial clock (SCK1) output SCK1)
2 3 8 2 8
Serial input/output SDIO1) (SDIO1)
Serial output counter OTC0 OTC3) (OTC0 to OTC3) Serial input counter (ITC0 to ITC3) ITC0 ITC3)
SO8
HZ
SI0
SI1
Data input
SI2
SI7
HZ
SO7
SO0
SO1
Data output
SO7
SOS= "0" setting SOS="0"
SOS="1"
HZ
STP= "1" STP="1" execution

SOS= "0" SOS="0" setting STP= "1" execution STP="1"

Issue of interruption
FF Reset="1" FF Reset= "1" execution SOS="1" SOS= "1" setting
Issue of interruption
Issue of interruption
Serial input counter (ITC0 ITC3) ITC0 to ITC3)

FF Reset= "1" FF Reset="1" execution SOS="0"
Execution of instruction
BUSY1
RXF/F
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(2) Example of serial mode setting in the 2-wire mode
Setting bit M0, M1 CK0, CK1, OSC0, OSC1 MASTER POL NchS SIS STPS SWENA MSB SOS STA0~3 STP0~3 PSEL, SIO 2-wire setting (M0 = 0, M1 = 1) Serial clock frequency setting
Condition setting data
Master setting (MASTER = 1): Refer to an example of master operation timing. Slave setting (MASTER = 0): Refer to an example of slave operation timing. Serial clock stop state = H Data output at the falling edge and data input at the rising edge (POL = 1) N-ch open drain setting (NchS = 1) Setting of SDIO pin to serial input (SIS = 0) Setting of stop condition to input counter Stop weight enabled (SWENA = 1) Output beginning with the most significant bit (MSB = 1) Data output: SOS = 1, Data input: SOS = 0 Serial input/output start data: 7h Serial input/output stop data: Eh Select N-ch open-drain pin (SDIO2, SCK2) (PSEL = 1, SIO = 1) (STPS = 1)
Stop Start condition condition
Serial clock (SCK2) SCK2) Serial input/output SDIO2) (SDIO2)
STP= "1" execution: Execution STP="1" of internal initialization (Stop condition is outputted in the master mode)
SCK"L" SCK pin outputs the "L" level to forcibly stop the serial clock
Stop condition
SI7/SO7
SI6/SO6
SI0/SO0
SIF/SOF ACK
SI7/SO7
SI6/SO6
SI0/SO0
SIF/SOF ACK
SOS= "1" setting Master mode: SOS="1" SOS="0" Slave mode: SOS= "0" setting
Data output: SOS= "1" setting SOS="1" Data input: SOS= "0" setting SOS="0"
TSTA1="1" TSTA1= "1" execution (in the master mode)
TSTA2= "1" execution TSTA2="1" (in the master mode)
F/F Reset= "1" execution Reset="1" SOS= "1" setting Master mode: SOS="1" SOS="0" Slave mode: SOS= "0" setting
F/F Reset= "1" execution F/F Reset="1"
Execution of instruction Serial output counter OTC0 OTC3) (OTC0 to OTC3) Serial input counter ITC0ITC3) (ITC0 to ITC3)
BUSY1
E
F
F
STP="1" STP= "1" execution mode) (in the master
Issue of interruption
Issue of interruption
E
E

F

F
E
BUSY2
RXF/F
Note:
The start condition (STA1 = "1") cannot be outputted at the ACK input/output timing during 2-wire operation (BUSY2 = "1") in the master mode. Output the stop condition, and then the start condition.
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(3) Example of UART mode setting
Setting bit M0, M1 CK0, CK1, OSC0, OSC1 MASTER POL NchS SIS STPS SWENA MSB SOS STA0~3 STP0~3 PSEL, SIO UART setting (M0 = 0, M1 = 1) Transmission rate setting Master setting (MASTER = 0) Serial clock stop state = H Data output at the falling edge and data input at the rising edge (POL = 0) N-ch open drain setting (NchS = 1) Setting of serial data pin to RX pin (SIS = 0) Setting of stop condition to input counter Stop weight disabled (SWENA = 0) Output beginning with the least significant bit (MSB = 0) Data output (SOS = 1) Serial input/output start data: 0h Serial input/output stop data: 9h Select N-ch open-drain pin (TX2, RX2) (PSEL = 1, SIO = 1)
tsck
Receiving (RX)
Condition setting data
(STPS = 1)
RX
SI0
Maximum tsck/8
SI1
SI5
SI6
tsck/8
tsck SO0 SO1
Sending (TX) (TX)
Receiving (RX) (RX)
Sending (TX) TX
SO9=1
SO6 SO7 SO8 SO9 =1 =1
Pulse widths of tsck/4 or below is not considered as received tsck/4
STP=1 execution STP=1
TSTA1=1 TSTA1=1 execution Issue of interruption
F/F Reset=1
Issue of interruption
Serial output counter (OTC0 to OTC3) OTC0 OTC3) Serial input counter (ITC0 to ITC3) ITC0 ITC3) BUSY1

RX F/F
Note: Note:
When a pulse width of tsck/4 or below is inputted during receiving (RX), the start of receiving will be cancelled. The UART circuit has a data judgment circuit. When receiving starts, the data judgment circuit outputs a 3-pulse data judgment pulse in the data position to judge the RX pin state. When at least two of these pulses record the same data, the received data is read as the serial data input. In other words, if noise occurs in one pulse in the pulse output position, the data can be received normally.
tsck
Receiving (RX)
RX
SI0
SI1
Data judgment pulse
Note:
This example shows sending and receiving without parity. The SO8 bit output is outptted as the stop bit. In the specification with parity, the SO8/SI8 bits can be assigned to parity. However, if transmission (TX) starts immediately after the issue of interruption, the stop bit width cannot be secured. In this case, after the interruption is issued, allow the operation to wait for a stop bit width or more before sending is executed. UART of this product supports the full/duplex specification. If sending and receiving operations are executed at the same time, they can be carried out normally. However, interruption is issued when either operation is completed and the BUSY1 bit becomes "0". Determine receiving operation using the RX F/F bit.
Note:
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1-3. Serial Clock Timing
Serial clock (SCK) SCK) Serial output (SDIO) SDIO)
TpL
TpLH
TpHL
TpH
Serial clock SCK) (SCK) Serial output (SDIO) SDIO)
TpLH pulse width (TpL/TpH):2.5s (minimum) Minimum TpL/TpH) 2.5s (TpLH/TpHL) 50ns Transmission delay time (TpLH/TpHL): 50 ns (standard)
TpHL
2. Serial Interface Configuration
High-speed oscillator 75kHz Low-speed oscillator M0, M1, OSC0, OSC1, SWENA M0,M1,OSC0,OSC1,SWENA (Xout2) clock (Xout2) 75(Xout1) kHz (Xout1) TSEL, SIO, STP, FF Reset TSEL,SIO,STP,FF Reset
Serial clock generator/ / Timing circuit Matched signal
BUSY1,BUSY2 BUSY1, BUSY2 SOERR SOERR
SO0~9, SOE/F SO0~9,SOE/F
STPS STPS
MASTER
SCK/RX SCK/RX POL POL
Selector
OCT0-OCT3 OCT0-OCT3
Serial output counter
Selector
SOS
SDIO/TX SDIO/TX
RX UART RX UART circuit
RX RX F/F F/F
MSB
STA0-STA3 STA0-STA3 Serial input counter ICT0-ICT3 ICT0-ICT3
STP0-STP3 STP0-STP3
SI
Selector I/O control
SIS UART UART Output data Input data
Decoder
Serial input latch
SI0~9, SIE/F SI0~9,SIE/F
Note: Note: Note:
When the serial interface function is working, the serial input-only pin (SI) can be used as an I/O port. To use it as the SI pin, you need to set the I/O port to input. All the serial interface pins are Schmitt input. When the serial interface function is used and the I/O port input is enabled to break, the wait or clock stop instruction will be released due to changes in serial input. Note that this requires input setting from the I/O port control and reading of the I/O port input before execution of the instruction. When the clock stop is released, CPU execution will be started after 100 ms of standby. When the serial interface function is used, I/O port 3 can be set to a pull-up/pull-down state.
Note:
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Comparator
TC9349AFG
Pulse Counter
The pulse counter is the 8-bit up/down counter that can detect the clock number through the CMOS input from PCTRin (P3-3) pin. It can be used for counting and detection of tape running.
1. Pulse counter control ports and data ports
Pulse counter control 1 Y1 Y2 Y4 Y8
L2B
POS
NEG
DOWN
*
Up/down setting of 8-bit up and down counter 8/ 0: Up 0 count operation 1: Down count operation
1
Counter input edge setting for input pin (PCTRin pin) (PCTRin)
POS 0 1 0 1 NEG 0 0 1 1 PCTRin P3-3/PCTRin P3-3
Input edge
Rising edge
Falling edge
Both edges
Pulse counter control 2 Y1 L2C Y2 Y4
*
Y8
*
CTR OVER RESET RESET
Overflow detection F/F reset F/F OVER F/F is reset each time "1" is set "1"OVER F/F
Pulse counter reset 8-bit up and down counter is reset each time "1" is set
"1"8
K2B Y1 Y2
P 0 P 1
Y4
P 2
Y8
P 3
K2C Y1 Y2
P 4 P 5
Y4
P 6
Y8
P 7
K2D Y1 Y2
OVER 0
Y4
0
Y8
0
20 LSB
Pulse counter data
27 MSB Overflow detection 0 Counter measured value 0: 28-1 28-1 8 1: 28() 1 Counter measured value 2 (Overflow state)
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The pulse counter measures the number of pulses of the input of PCTR in the (P3-3) pin. The POS and NEG bits specify the input pin clock edge from the rising edge, the falling edges and both edges. This bit is fixed in the normal operation. The DOWN bit sets the up or down of the 8-bit counter. When this bit is set to "0", the up count operation becomes active. When this bit is set to "1", the down count operation becomes active. Up and down counts can be switched freely. If the clock edge is inputted during execution of the switch instruction, this count will be cancelled, please remain aware of this. 8 The OVER F/F bit is set to "1" when an edge of 2 or higher is inputted. To activate a count operation of 8 bits or more, this OVER F/F bit is detected to add or subtract the number of times of overflow on the data memory. After detection is carried out by this bit, set the OVER RESET bit to "1" to reset OVER F/F. The CTR RESET bit resets the 8-bit counter only. The counter will be reset each time this bit is set to "1". Counter data is loaded into the data memory in binary format. Pulse counter control and data loading are accessed by the OUT2/IN2 instruction with [CN = BH~DH] specified in the operand.
2. Pulse Counter Circuit Configuration
OVER RESET CTR RESET DOWN POS NEG CPU operation clock Input enable signal
F/F
8-bit up/down counters 8 bit up/down counter
Selector Selector
Edge Detection Edge Detection
40
P3-3/PCTRin
OVER F/F
PC0 PC7
3. Example of Pulse Counter Timing
CTR/OVER CTR /OVER RESET execution RESET
Data set to pulse counter control bit DOWN
DOWN bit
OVER OVER RESET RESET execution
Set DOWN bit "1" "1"
DOWN
Pulse width 30 us (minimum) (in CPU 30us75kHz 75 kHz CPU operation)
CTR in
CTR in input
data Counter
OVER OVER F/F F/F
01H
02H
03H
FFH
00H
01H
02H
N
N+1
N-1
N-2
Note: The CTRin input pin is the Schumitt input. Note: The pulse counter uses the CPU operation clock (75 kHz of low-speed clock) to determine the sampling and edges. Input a pulse width of at least twice the CPU operation clock. Note: When the pulse counter function is used and the I/O port input is enabled to break, the wait or clock stop instruction will be released due to changes in serial input. Note that this requires input setting from the I/O port control and reading of the I/O port input before execution of the instruction. he first pulse is not counted. When the clock stop is released, CPU execution will be started after 100 ms of standby. Note: When the pulse counter function is used, I/O port 3 can be set to the pull-up/pull-down state.
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Buzzer Output
Buzzer output can be used for emitting beeps for acknowledgement and alarm purposes during key operations and when in tuning scan mode. The type of buzzer can be selected from combinations of four output modes and eight frequencies.
1. Buzzer Control Ports
Buzzer output control 1 Y1 Y2 Y4 Y8 L15(0)
BF0 BF1 * BEN
selection data
Buzzer frequency
Buzzer output enable bit 0: Buzzer output Prohibitiond ("L" level when POL= "0", "H" levelPOL="1""H") 0 (POL="0""L" when POL= "1") 1: Buzzer output enabled
1 BF0 0 1 0 1
BF1 0 0 1 1
Buzzer frequency
1kHz 1.56kHz 2.08kHz 3kHz
Duty 2/3 1/2 2/3 2/3
2/3 duty has the ratio of "H" level to "L" level of 2:1 when POL= "0". Note: POL="0""H""L" It is reversed when POL= "1". POL="1"
Buzzer output control 2 Y1 Y2 Y4 Y8
L15(1)
BM0
BM1
BUZR ON
POL
Buzzer output mode
Buzzer output logic setting 0: Positive logic output. The buzzer frequency is outputted in the positive logic from 0 "L" the "L" level. 1 "H" 1: Negative logic output. The buzzer frequency is outputted in the negative logic from the "H" level. Selection of I/O port 4 P4-2 or buzzer output I/O4P4-2 0: 4 (P4-2) 0Select I/O portoutput I/O4(P4-2) 1: Select buzzer 1
BM1 0 0 1 1
BM0 0 1 0 1
Buzzer output mode Mode A A Mode B B 10H C 10-Hz intermittent output Mode C 10-Hz intermittent output at 1 Hz intervals D 10H 1H Mode D Single output Continuous output
Y1 K26
Y2
BUZR 10Hz
Y4
Y8
Buzzer dedicated 10-Hz timing operation monitor 10Hz Note: BEN"1"100Hz10Hz When the BEN bit is set to "1", 10 Hz operates at the base clock of 100 Hz. Refer to the 10-Hz timer when Mode D is selected.
D Hz
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The buzzer output is also used as the P4-2 I/O port. It can be switched to buzzer output by setting the BUZR ON bit to "1" and setting the P4-2 I/O control port to output. Once the buzzer frequency, mode and logic are specified, set the buzzer enable bit to "1", and the buzzer will be emitted. Set the buzzer enable bit to "0" for condition setting. In the continuous output mode (Mode A), when the buzzer enable bit is set to "1", the buzzer frequency will be outputted continuously. Set the bit to "0" to stop the buzzer output. In the single output mode (Mode B), a 50-ms buzzer will be outputted and stopped each time the buzzer enable bit is set to "1". In this mode, the buzzer output time can be extended by 50 ms to issue a 100-ms buzzer by setting the buzzer enable bit to "1" again during output of the 50-ms buzzer. The buzzer output time can be further extended to 150 ms by setting the bit to "1" again during extended 50 ms. This facilitates adjusting the buzzer output time. In the 10-Hz intermittent output mode (Mode C), the cycle of 50-ms buzzer ON and OFF respectively will be repeated continuously by setting the buzzer enable bit to "1". Set the bit to "0" to stop the buzzer output. In the 10-Hz intermittent output mode at 1Hz intervals (Mode D), when the buzzer enable bit is set to "1", the cycle of 50-ms buzzer ON and OFF respectively will be outputted for 500 ms, the buzzer will be stopped for 500 ms and again the cycle of 50-ms buzzer ON and OFF will be outputted for 500 ms. These cycles are repeated until the buzzer output is stopped by setting the bit to "0". In Modes B, C and D, a 50 ms buzzer will be outputted and stopped even if the enable bit is set to "0" to stop the buzzer in the buzzer output state. The buzzer output state can be checked based on the details of the BUZR 10 Hz bit. When the BUZR 10 Hz bit is set to "0", it shows the buzzer output state. When the bit is "1", it shows the buzzer is stopped. Refer to the 10 Hz timer in Mode D. Buzzer control can be accessed at OUT1 instruction data port 6.
2.
Buzzer Circuit Configuration
1Hz BUZR10Hz Selector Selector
00Hz
ModeD 1Hz
Divider Divider (1/10) (1/10)
1kHz
Selector Selector
BUZR outputcircuit BUZR output circuit
40 BUZER(P4-2)
3kHz
~
BF0, BF1 BEN
BM0~BM2
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3. Buzzer Output Timing
Buzzer frequency
"1" "1" "0"
Data set to BEN bit
(A) Buzzer output (Mode A)
BUZR 10 BUZR 10H Hz
10ms 10 ms max.
Extended by 50 ms N"1"50ms B by setting the BEN bit again to "1" during buzzer output
(B) Buzzer output (Mode B)
50ms
BUZR 10 BUZR 10H Hz
10 ms max. 10ms Buzzer frequency
(C) Buzzer output (Mode C)
50ms
output period
Stop period
C (D) Buzzer output (Mode D)
Stop period
500ms
500ms
Output period
Note: To output the buzzer, set P4-2 to the output state (set the I/O control port to "1"). Note: The buzzer is stopped compulsory by setting BEN = 0. Note: When the frequency setting is changed during buzzer output in Mode B, it will be updated and the 10-Hz timing change points changed.
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LCD Driver
The LCD driver is also used as an I/O port, and it allows a maximum of 72 segments to turn on. When the LCD driver is enabled, I/O port 10 is switched to COM1 to COM4 pins and I/O port 12 is switched to S1 to S4 pins. Each of the 14 pins of I/O ports 13, 14, 15 and 16 can be set to segment pin output. The driving method of the LCD driver can be selected from 1/4 duty, 1/2 bias (frame frequency 62.5 Hz) and 1/3 bias drive (frame frequency 125 Hz). The LCD driver is built-in the constant voltage for display (VEE = 1.5 V) and the doubler circuit (VLCD = 3.0 V) that increases the display voltage. The LCD driver ensures a stable LCD display; even if the supply voltage fluctuates. ( Refer to the section on the CD driver doubler circuit.) In the 1/2 bias mode, the LCD driver provides common output at three potentials VLCD, VLCD x 1/2 and GND, and provides segment output at two potentials VLCD, GND. In the 1/3 bias mode, the LCD driver provides common and segment outputs at four potentials VLCD, VLCD x 2/3, VLCD x 1/3 and GND.
1. LCD Driver Ports
LCD driver control LCD
Y1 L17
DISP OFF
Y2
LCD OFF
Y4
BIAS
Y8
*
Selection of LCD drive LCD method
01/2 0: 1/2 bias 11/3 1: 1/3 bias 0LCD 1I/O 1: I/O port
0: LCD driver
LCD off control bit
LCD display off control bit
0 0: Set data output 1 1: Off data output
L/K1A Y1 Y2
SEL1 SEL2
Y4
SEL4
Y8
SEL8
Data select L13 (Data port L13(4)4) Y1 Y2 Y4 Y8
COM1 COM2 COM3 COM4
L14 (Data port 5) L14(5) Y1 Y2 Y4 Y8
COM1 COM2 COM3 COM4
(4) (5) (6)

COM1 COM2 COM3
(0) (1) (2) (3) (4) COM4 (5)

Segment data 0: Turn off 1: Turn on
(F)
Segment select
Switching between the segment output and I/O port I/O 0: 0:I/O I/O port 1: 1: Segment output
(C) (D) (E) (F)
Note:
Segment data controls the segments on/off corresponding to the common and segment outputs.
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The LCD driver control ports are assigned to data control ports 4 and 5; as selected at the select port. These ports are accessed by using the OUT1 instruction with [CN = 3H, 4H] specified in the operand. LCD driver segment data The LCD driver segment data is specified at data ports 4 and 5 (L13 and L14). When the segment data port is set to "0", the LCD display turns off. When the port is set to "1", the LCD display turns on. LCD OFF bit The LCD OFF bit controls switching between the LCD output pin and the I/O port. After a reset, the pin that serves as both an I/O port and LCD driver is in the I/O port state. Set this bit to "0" when using the LCD driver function. When the LCD driver function is enabled, four of the I/O port pins P10-0 to P10-3 are switched to the COM1 to COM4 output pins, and four pins P12-0 to P12-3 are switched to the S1 to S4 output pins. Note: This bit is set to "1" after a system reset.
DISP OFF bit The DISP OFF bit allows all the LCD display to turn off without setting segment data. Setting this bit to "1" turns all the LCD display off. At this time, the segment data is retained. When the DISP OFF bit is set to "0", the previous display will appear on the LCD as it is. Note: Note: Note: Segment data can be rewritten during DISP OFF. After the CKSTP instruction is executed, the DISP OFF bit is set to "1". After the CKSTP instruction is released, set the DISP OFF bit to "0" as required. This bit is reset to "0" after system reset.
BIAS bit The BIAS bit selects the liquid crystal driving method. Set this bit to "0" to select the 1/2 bias method (frame frequency 62.5 Hz) or set to "1" to select the 1/3 bias method (frame frequency 125 Hz) Note: Note: In the 1/3 bias mode, the consumption current becomes about 100 A larger than that in the 1/2 bias mode. This bit is reset to "0" after a system reset.
Segment select port Each of the 14 pins of I/O ports 13 to 16 can be switched to a segment pin. Set the bit corresponding to each segment to "1" to use the pin for segment output, or set to "0" to use the pin as an I/O port. The S5 to S8 bits correspond to pins P13-0 to P13-3 respectively. The S9 to S12 bits correspond to pins P14-0 to P14-3 respectively. The S13 and S14 bits correspond to pins P15-0 and P15-1 respectively. The S15 to S18 bits correspond to pins P16-0 to P16-3 respectively. Note: Segment output and I/O port setting can be made regardless of the LCD off control bit (LCD OFF). However, the pins that have been set to segment output require setting of the LCD off control bit to the LCD driver to enable segment output. Pins S21 and S22 are also used as high-speed oscillator pins. When they are set to high-speed oscillator pins, the high-speed oscillator function has priority and this port becomes to "don't care" state. This bit is reset to "0" after a system reset.
Note:
Note:
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2. LCD Driver Configuration
P16-3/S18/Xout2 P16-2/S17/Xin2 P10-0/COM1 P10-1/COM2 P10-2/COM3 P10-3/COM4
P16-0/S15
6
7
8
9
10
15
16
17
18
19
20
33
34
P16-1/S16
P12-0/S1
P12-1/S2
VCPU
VLCD
VEE
C3
C4
35
36
VLCD VLCD doubler circuit
Constant-voltage circuit

I/O10 I/O port 10 1 DISP OFF LCD OFF VLCD
VLCD x1/2 VLCDx1/3 VLCDx2/3
I/O12 16 I/O port 12 to 16
High-speed oscillator
Common output circuit
Segment driver Segment data
VEE BIAS
Bias circuit
Note: Note:
After a system reset, all the pins that also serve as the LCD driver pins will be the I/O port input state. The LCD driver pins are also used as I/O ports and high-speed oscillator pins.
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3. LCD Driver Operation Timing
LCD output waveform in the 1/2 bias mode (BIAS bit= "0") In the 1/2 bias mode, the potential of the LCD driver waveform is outputted as VLCD and GND and the VEE level is outputted at a frame frequency of 62.5 Hz.
COM1
COM2
Segment data 1(L13, 1(L13L14) L14) Y1 Y2 Y4 Y8
0 (S1) COM1 COM2 COM3 COM4 1 0 1 0
Example of segment data
COM3
S1 S2
COM4
1 (S2)
COM1 COM2 COM3 COM4 1 1 0 1
(L/K1A) Data select(L/K1A)
DISP OFF 2ms COM1 16ms(62.5Hz)
VLCD(3V) VEE(1.5V) GND VLCD(3V)
COM2
VEE(1.5V) GND VLCD(3V)
COM3
VEE(1.5V) GND VLCD(3V)
COM4
VEE(1.5V) GND VLCD(3V)
S1
GND VLCD(3V)
S2
GND VLCD
COM1-S1 COM1-S1 (ON waveform)
(ON)
GND
-VLCD VLCD
COM2-S1 COM2-S1 (Off(OFF) waveform)
GND
-VLCD
Note: Note:
Setting the DISP OFF bit to "L" causes the common output to revert to the VLCD x 1/2 level and turns all the display off. All the common and segment outputs are fixed to the "L" level in the clock stop mode and for 100 ms after this is released.
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LCD output waveform in the 1/3 bias mode (BIAS bit= "1") The potential of the LCD driver waveform is outputted as VLCD and GND, and the intermediate potential levels, 1/3 and 2/3 of potential VLCD are outputted at a frame frequency of 125 Hz.
COM1
COM2
Example of segment data 1(L13 L14) Segment data 1(L13, L14) Y1 Y2 Y4 Y8
0 (S1) COM1 COM2 COM3 COM4 1 0 1 0
COM3
S1 S2
COM4
1 (S2)
COM1 COM2 COM3 COM4 1 1 0 1
Data select(L/K1A) (L/K1A)
DISP OFF 1ms COM1 8ms(125kHz)
VLCD VLCDx2/3 VLCDx1/3 GND VLCD VLCDx2/3 VLCDx1/3 GND VLCD VLCDx2/3 VLCDx1/3 GND VLCD VLCDx2/3 VLCDx1/3 GND VLCD VLCDx2/3 VLCDx1/3 GND VLCD VLCDx2/3 VLCDx1/3 GND VLCD
COM2
COM3
COM4
S1
S2
COM1-S1 COM1-S1 (ON waveform) (ON)
VLCDx1/3 GND VLCDx1/3 VLCD VLCD
COM2-S1 COM2-S1 (Off waveform) (OFF)
VLCDx1/3 GND VLCDx1/3 VLCD
Note: Note: Note: Note:
Setting the DISP OFF bit to "1" outputs unselected waveforms as common and segment outputs. All the common and segment outputs are fixed to the "L" level in the clock stop mode and for 100 ms after this is released. In the 1/3 bias mode, the frame frequency is twice as high as that in the 1/2 bias mode. In the 1/3 bias mode, the consumption current becomes about 100 s larger than that in the 1/2 bias mode.
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A/D Converter
The A/D converter has four channels with 6-bit resolution, and can be used for measuring electrical field strength, measurements of battery and cell voltages and key input using ladder resistance.
1. A/D Converter Control Port and Data Port
Y1 L23 AD SEL0 Y2 AD SEL1 Y4 AD SEL2 Y8 STA
A/D converter start bit A/D conversion is implemented each time this is set to "1" Selection of A/D input pin SEL2 0 0 0 0 1 SEL1 0 0 1 1 * SEL0 0 1 0 1 * AD input ADin1 ADin2 ADin3 ADin4 VEE/2
K20 Y1 AD0 Y2 AD1 Y4 AD2 Y8 AD3
K21 Y1 AD4 Y2 AD5 Y4 BUSY Y8 0 A/D converter operation monitor
LSB
A/D conversion data
MSB
0: A/D operation finished 1: A/D converting
The A/D converter operates using a serial comparison system with 6-bit resolution. The standard voltage for A/D conversion is the internal power supply (VDD), which is divided into 64 parts. The divided voltage is compared to the A/D input voltage and the data is outputted to the A/D conversion data port. The A/D conversion input uses the multiplex method; consisting of four channels of external input pins (ADin1 to ADin4 pins) and the half potential of the VEE pin voltage. The desired method can be selected by the AD SEL0 to 2 bits. The A/D converter carries out A/D conversion each time the STA bit is set to "1", and finishes operation after 6 machine cycles (240 s). Completion of the A/D converter operation can be determined by checking the BUSY bit. Once the A/D conversion is finished, the A/D conversion data is taken into the data memory. The results of the A/D conversion can be obtained by performing the following calculation: VDD x n - 0.5 64 (63 > n > 1) < A/D input voltage < VDD x == = = n + 0.5 64 (62 > n > 0) ==
(n: A/D conversion data value [decimal scale]) VEE/2 for A/D input is used for battery detection. The VEE potential is normally 1.5 V. The half potential of the VEE pin voltage, 0.75 V, is selected for A/D input. Through the A/D conversion of this potential, the reference potential, VDD, can be detected. When the VDD potential is 1.5 V, the A/D conversion data is 20H. As the VDD potential becomes lower, the A/D data becomes higher. When the VDD potential is 0.75 V, the A/D conversion data is 3FH. This control is accessed by using the OUT2/IN2 instructions with [CN = 3H, 4H] specified in the operand.
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2. A/D Converter Circuit Configuration
Comparator A/D conversion latch A/D conversion data
Sample hold
11 12 SEL0~2 BUSY 13 14
ADin1 (P6-0) ADin2 (P6-1) ADin3 (P6-2) ADin4 (P6-3)
AD0 AD5 ~
VDD R 3R/2 Decoder R/2 R R
Control circuit STA BUSY
VDB (VDD doubled voltage)
VEE constant-voltage circuit
9
VEE
BUSY
The A/D converter consists of a 6-bit D/A converter, a sample hold, a comparator, an A/D conversion latch and a control circuit. The 6-bit D/A converter and the comparator operate only when the BUSY bit is "1". Therefore, the A/D converter consumes no current when it is not operating. The half potential of VEE constant voltage can be selected as the A/D input. The A/D converter operates on the doubled voltage VDB (VDD x 2). Note: Set to "1" the I/O port -6 (N-ch open-drain) output data corresponding to the A/D input pin to be used, to use the pin in the input state. Note: The VEE contant-voltage potential is used for the LCD driver driving voltage and the reference voltage of reduced-voltage detection circuit for the DC-DC converter for CPU and VT. Note: Voltage of 0 V to VDB pin level can be applied to the A/D input pin.
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Programmable Counter
The programmable counter consists of a 2-modulus pre-scalar, a 4-bit and 12-bit programmable counter and a port that controls these elements. The programmable counter stops operation in the PLL off mode, and operates in the PLL on mode respectively. The radiation and consumption current can be reduced when the programmable counter is used in combination with the 1-chip tuner with a built-in 1/16 pre-scaler. The frequency divided by the programmable counter is inputted to the phase comparator, and the phase difference from the reference frequency is outputted from the phase comparator. The internal clock of the programmable counter can also be used to detect phase difference of the phase comparator and the doubler clock for DC-DC converter for VT. ( Refer to the sections on Reference frequency divider, DC-DC converter for VT and Phase comparator.)
1. Program Counter Control Port
The PLL mode selection port is used for setting the frequency dividing method, while the programmable counter port is used for setting the frequency division number.
Selection of PLL mode Y1 L15(8) HF Y2 Y4 Y8 O
Setting the frequency dividing method
0LF mode 1HF mode
Programmable counters 1 to 4 L15(A) Y1 P0 Y2 P1 Y4 P2 Y8 P3 L15(B) Y1 P4 Y2 P5 Y4 P6 Y8 P7 L15(C) Y1 P8 Y2 P9 Y4 Y8 L15(D) Y1 Y2 Y4 Y8
P10 P11
P12 P13 P14 P15
LSB
Setting the frequency division number of the programmable counter
MSB
Y1 L16(F) 11(F) TA0
Y2 TA1
Y4 TA2
Y8 TA3
PLL amplifier setting register
Set ALL "1" (FH)
The selection of the PLL mode and setting of the frequency division number of programmable counter are assigned to data port 6 that has been selected at the select port. These controls are accessed by using the OUT1 instruction with [CN = 5H] specified in the operand. There are two types of frequency division methods; the direct frequency division method (LF mode) and the pulse swallow method (HF mode). Select a method depending on the frequency to be used and the frequency division number that has been set. The programmable counter has 12 bits (P4 to P15) in the LF mode and 16 bits (P0 to P15) in the HF mode. The frequency division number is specified by writing it to the MSB bit (L15(D). Once the MSB bit is set, all the data of P0 to P15 will be updated. Therefore, the MSB bit must be accessed and specified last, even when part of the data is changed. The PLL input (OSCin) has an input amplifier. Set this amplifier gain at the PLL amplifier setting registers. Set all of these registers to "1" (FH). Note: Note: Note: Set the Y8 bit of the PLL mode select port (L15(8)) to "0". All the PLL amplifier setting registars are set to "1" after a system reset. In the PLL amplifier setting registers, the TA0 and TA1 bits are for the OSCin input amplifier gain setting and the TA2 and TA3 bits are for the IFin input amplifier gain setting respectively.
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2. Setting the Frequency Dividing Method and Gain of The Programmable Counter
Using the HF bit, select the pulse swallow or direct frequency division methods; depending on the received frequency. The programmable counter is used in combination with the 1-chip tuner with a built-in 1/16 or 1/8 pre-scaler. Usually, use the tuner to input the local oscillation frequency, which is then inputted to the OSCin input in the MW/LW/SW wavebands. The tuner local oscillation frequency is divided into 16 or 8 parts and the divided frequency is inputted to the OSCin input in the FM/TV band mode. The OSCin input has an input amplifier that allows small-amplitude operation. The input amplifier has the registers (L16(F), K11(F)) to adjust the amplifier gain. Set all of these registers to "1" (FH).
Frequency dividing method Direct frequency dividing method Pulse swallow method (1/1516) OSCin operation input frequency range 0.5~4 MHz 1~30 MHz Example of receive band MW/LW SW/FM/TV Frequency dividing range 10H~FFFH (16~4095) 210H~FFFFH (52865535)
Mode
HF
LF HF
0 1
Note: The local oscillation input is common to each mode and is inputted to the OSCin pin.
3. Setting the Frequency division number
Set the frequency division number for the programmable counter at P0 to P15 bits in the binary format.
* Pulse swallow method (16 bits)
MSB P15 P14 P13 P12 P11 P10 2
15
LSB P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2
0
Frequency division setting range (n = 210H~1FFFFH (528~65535))
* Direct frequency division method (12 bits)
MSB P15 P14 P13 P12 P11 P10 2
11
LSB P9 P8 P7 P6 P5 P4 2
0
P3
P2
P1
P0
Frequency division setting range (n = 10H~1FFFH (16~4095))
don't care
Note: Note:
Set the frequency division value in consideration of the tuner pre-scaler frequency division. Set the frequency division number by writing it into the MSB bit (L15(D)).
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4. Programmable Counter Circuit Configuration
The circuit consists of an amplifier, 1/1516 2-modulus pre-scaler, a 4-bit swallow counter and a 12-bit binary programmable counter. When the HF mode is selected, the 1/1516 pre-scaler, the 4-bit swallow counter and the 12-bit binary programmable counter are used. When the LF mode is selected, only the 12-bit binary programmable counter is used. The OSCin input clock is supplied to the DC-DC converter for VT, and used as the doubler clock. The clock divided by the programmable counter is also supplied to the phase comparator and the IF counter. ( Refer to the sections on DC-DC converter for VT and Phase comparator.)
P0~P3 TA0, TA1
Amplifier
VPLL 50 OSCin 0.01 F 51
1/16 HF 1/1516 1/15 LF HF
4-bit swallow counter Preset 12-bit programmable counter
To phase comparator
P4~P15 To DC-DC converter for VT To phase comparator To IF counter
Note: The programmable counter uses the VPLL pin power supply. This power supply can be supplied regardless of the power supply level of the VDD/VCPU pin. In the PLL off mode, the VPLL pin power supply can be turned off. The programmable counter setting registers use the VCPU pin power supply, so that the contents of the registers are retained after the VPLL pin power supply is turned off. Note: The OSCin pin has an amplifier that allows small-amplitude operation with coupled capacitor. The OSCin input is subject to high impedance in the PLL off mode.
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Reference Frequency Divider
The external 75 kHz crystal oscillation frequency is divided to generate the following ten types of PLL reference frequency signals; 1 kHz, 1.39 kHz, 1.56 kHz, 2.78 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25 kHz, 12.5 kHz and 25 kHz respectively. These signals can be selected by the reference port data. The selected signal is supplied as a reference frequency for the phase comparator as described below. The PLL on/off is controlled by the contents of the reference port.
1. Reference Port
This is an internal port for selecting ten types of reference frequency signals. This port is located in data port 6 as selected at the select port, and can be accessed by using the OUT1 instruction with [CN = 5H] specified in the operand. When the reference port is set to all "1", all the programmable counters, IF counters, reference counters and the phase comparator will be stopped and enter the PLL off mode. When the reference port setting is set, the frequency division setting data for the programmable counter will be updated. Therefore, the frequency division number of the programmable counter must be determined before setting the reference port.
Y1 L15(E) R0 Y2 R1 Y4 R2 Y8 R3 R3 0 Reference frequency select code 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 A B C D E F Oscillation frequency 1 kHz 1.3889 kHz 1.5625 kHz 2.7778 kHz 3 kHz 3.125 kHz 5 kHz 6.25 kHz 12.5 kHz 25 kHz Prohibition Prohibition Prohibition Prohibition Prohibition PLL off mode
Note: Note:
After a system reset, this port is set to all "1" and becomes to PLL off mode. When the pin input permission is set by using the ENA bit, the PLL off mode becomes the input or the PLL off mode as shown above.
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Phase Comparator and Lock Detection port
The phase comparator compares the reference frequency supplied from the reference frequency divider and the programmable counter divided frequency output to determine the phase difference and outputs errors. It then controls the voltage control oscillator (VCO) through the low-pass filter to match the frequency and phase difference of these two signals. There are two pins available for the phase comparator, each including individually adjustable output resistance. This resistance can be set to three types, namely 5, 50 and 100 k. It also includes automatic switching by detection of the phase difference, the N-channel transistor for an LFP amplifier that withstands 5.5 V and the external charge pump output mode. The phase comparator and the charge pump output use the DC-DC converter power supply (VDB: VDD x 2) for CPU. Note that the phase comparator output pins (DO1/2) can be used as general-purpose output ports by using the DO control port.
1. Phase Comparator (DO) Control Port and Unlock Detection Port
DO1 control
DO1 Y1 Y2 Y4
R0 R1 M0
DO1/DO2 output state setting DO1/DO2
Y8
M1
M1 0 0 1 1
M0 0 1 0 1
Output state Phase comparator output "L" "L" level output "H" "H" level output High impedance
L24
OT OT output
DO1/DO2 output resistance setting DO1/DO2 DO2 DO control 1
R1 R0 0 1 0 1
DO output resistance DO
0 5k 50k 100k
Y1 L25
R0
Y2
R1
Y4
M0
Y8
M1
0 0 1 1
DO2 control 2
DO Y1 Y2 Y4
ENA CK0
Y8
CK1
L26
AUTO
DO2 difference detection clock
CK1 0 0 1 1 CK0 0 1 0 1
Phase difference (fd) detection clock (fd)
Selection of DO2 output resistance phase
OSCin/2 OSCin/4 OSCin/8 OSCin/16
Permission of phase difference detection
0 0: Prohibition 1 1: Enabled
0: Prohibition 0 DO2 output resistance automatic DO2 1: Enabled switching control 1
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LPF ON
L27
UNLOCK RESET
PN
POL
Built-in LPF control LPF
0 0: Off 1 1: On
0: 0 Positive logic Selection of PN output PN logic Negative logic 1 1:
PN output control PN
0 0: Prohibition 1 1: Enabled
Unlock F/F and Unlock enable are reset each Unlock reset "1"F/F time the data is set to "1".
Y1 K27
F/F
Y2
ENA
Y4
Y8
Unfixed Unfixed
Unlock enable
0 PLL 0: PLL unlock detection standby 1 PLL 1: PLL unlock detection enabled
0: PLL lock state 0 PLL 1: PLL unlock state 1 PLL
Unlock detection bit
Note:
Y4/Y8 bits of the unlock port (K27) become unfixed.
The phase comparator control port and the unlock detection ports are accessed by using the OUT2 instruction with [CN = 4H, 5H, 6H, 7H] and the IN2 instruction with [CN = 7H] specified in the operand. These control bits are reset to "0" after a system reset. Output mode setting (M0 and M1 bits) The M0 and M1 bits are used for setting the phase comparator output (DO1/2 output pin) state. The phase comparator output, the "H" and "L" levels and high impedance (HZ) state can be set. Note: Note: If the PLL off mode is selected, the "HZ" will be retained in the phase comparator output state, and the "H"/"L" level will be retained when the "H"/"L" level is selected. When PN = "1" is selected, the PN output mode has the priority.
Output resistance setting (R0 and R1 bits) The R0 and R1 bits are used for setting the output resistance of the phase comparator output individually for DO1 and DO2 pins. They can be set to four states; the normal output buffer state, 5 k, 50 k and 100 k. Note: Note: The output resistance is set regardless of the output mode (M0, M1) and the PN output mode. Therefore, set these bits to "0" when the "H"/"L" level or the PN output mode is selected. When the DO2 pin is set to the automatic phase difference switching mode, the R0/R1 bits of DO2 control 1 becomes to the "don't care" state.
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Automatic phase difference switching mode (DO2 control 2 port: AUTO, ENA, CK0 and CK1 bits) The DO2 pin has an automatic phase difference switching mode that switches the output resistance automatically; depending on the phase difference. In this mode, the output resistance becomes higher as the phase difference pulse becomes shorter, and vice versa. In other words, the system operates with a higher resistance in the lock state and conversely, with a lower resistance in an unlocked state. By using this mode, the lock up time can be improved. When the ENA bit is set to "1", the phase difference detection operation is enabled. When the AUTO bit is set to "1", the DO2 output resistance switching is implemented. Phase difference detection is implemented using the operation clock from the programmable counter circuit. This clock counts the unlock state in the binary format. Four types of OSCin input, 1/2, 1/4, 1/8 and 1/16 can be selected for this clock. The output resistance setting time can be switched by switching the clock. This control selects the clock frequency using the CK0 and CK1 bits. Select the clock frequency depending on the lock up time. After locking, turn off automatic switching and set the output resistance to fixed settings (R0 and R1 bits) as needed.
Reference frequency (fr) Programmable counter output (fs) DO
DO output
Phase error
td=1/fd
Phase difference detection clock
DO2 output resistance state DO2
5 k
0k
100k
50k
Timing example 1
resistance value Output Phase difference resistance period
Timing example 2
CK1 0 0 1 1 CK0 0 1 0 1
Phase difference (fd) detection clock (fd)
frfs (Example-1) 0 0.5x 0.5x td 2x
frfs (Example-2)
OSCin/2 OSCin/4 OSCin/8 OSCin/16
100k 50k 5k 0k
0 td/2 0 1.5xtd td 2.5x 2xtd 2.5x
Note: Note:
When PN = "1" is selected, the PN output mode has priority. Effective only when the DO2 output mode setting is in the phase comparator output state.
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PN output mode (PN and POL bits) The PN output mode is available using an external charge pump. When this mode is selected, the two DO1/2 pins are switched to the P- and N-output pins. The P/N output logic can be reversed by using the POL bit. An example of the use of an external charge pump is shown below. Configure the circuit depending on your desired characteristics.
DC-DC converter
P
VDB VDB
Reference frequency
Programmable counter output
comparator
N
Phase
53
VT VCO To vari-cap of VCO
54
POL
Example of use of the external chargePN="1" PN= "1") pump (when Note: Note: Set the POL bit to "0" unless the PN output mode is selected. When the PN output mode is selected, the output will be CMOS output and the "H" level will be the VDB pin level outputp.
Built-in LPF amplifier (LPF ON bit) This amplifier incorporates the N-channel FET transistor for LPF. This transistor withstands 5.5 V and it can configure the voltage control oscillator (VCO) that can vary the VT within a range of 0 to 5.5 V. Setting the LPF ON bit to "1" turns the built-in LPF on. Pins DO2 and P9-1 are then switched to the FET gate input (Tin) and the FET drain pin (Tout) respectively. The DO2 phase comparator output is connected to the FET gate pin. The LPF can be configured only by connecting an external filter resistor and capacitor.
4.7k
VDB VDB
Reference frequency Programmable Tout
1000pF
VDB VDB
0.47uF
Tin
55
Phase comparator
54
VT
10k 0.01uF
VCO To vari-cap of VCO
counter output
Voltage of DC-DC converter for VT VTDC-DC
LPF ON="1" Configuration of built-in low-pass filter amplifier (when LPF ON= "1")
Note: Note: Note: Note: Note: When the built-in LPF is used, the DO2 output mode, resistor setting and the automatic phase difference switching mode are available. The Tout output withstands up to 5.5 V. Do not use voltages exceeding this limit. Set the resistance values for R0 and R1 depending on your desired characteristics. The filter circuit constants shown above are for reference only. Examine and design actual circuits according to the system band configuration and your desired characteristics. The Tout pin is also used as pin P9-0. When the built-in LPF is used, the P9-0 output data will be invalid.
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Unlock detection port (UNLOCK RESET, UNLOCK F/F and ENA bits) The unlock F/F detects the phase difference between the programmable counter frequency-divided output and the reference frequency at the timing with a phase shift of about 180. If the phases do not match, or are in an unlocked state, the unlock F/F will be set. Each time the unlock reset bit is set to "1", the unlock F/F will be reset. To detect the phase difference during the reference frequency cycle, it is necessary to provide an unlock F/F reset time no shorter than the reference frequency cycle before the unlock F/F is accessed. The enable bit is provided for this purpose. Make sure that the unlock enable is set to "1" before the unlock F/F is accessed.
2. Phase Comparator and Unlock Port Timing
Reference frequency
Programmable counter output
DO output DO Phase difference
Lock detection strobe Unlock reset execution F/F F/F Unlock Unlock enable
High impedance
"H" (VDB) "H" level "L"(GND) "L" level
When PN= POL="0" PN="1" "1" and POL= "0"
P(DO1) P output (DO1 pin)
"H" level (VDB) "H" (VDB)
"L" level (GND) "L"(GND)
"H" level (VDB) "H" (VDB) "L"(GND) "L" level (GND)
N output (DO2 pin) N(DO2)
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3. Phase Comparator and Unlock Port Circuit Configuration
VDB VDB
VDB VDB
Programmable counter output
Phase comparator
Decoder
Reference frequency
53 DO1/OT1/P
R0,R1
PN POL bits PN and POL UNLOCK ENABLE UNLOCK RESET
Decoder
UNLOCK F/F
VDB VDB
54 DO2/OT2/N/TIN
R0,R1
Selector
Programmable counter clock
Selector
Phase difference counter
LPF ON AUTO
P9-0 output data P9-0
55 P9-0/Tout
CK0,CK1
Note: The phase comparator circuit block uses the VDB power supply. Therefore, the VDB power supply level is outputted as the "H" level of the phase comparator output pin (DO).
Power supply (VDD) VDD)
0.47uF
470pF
To VCO vari-cap of VCO
VT
10K
1K
To VCO vari-cap of VCO
VT
4.7k
1000pF
DC-DC DC-DC converter
1uF
4.7K
0.01uF
0.01uF
54
220pF
DO2
Note DC-DC DC-DC converter
Example of external low-pass filter amplifier circuit
Example of built-in low-pass filter amplifier circuit
Note: The phase comparator pin has a built-in resistor. Add an output resistor if needed. Note: For details of the DC-DC converter, refer to the section on the DC-DC converter for VT. When the DCK1 internal doubler transistor is used for the DC-DC converter voltage, design the tuner circuit to widen the variable range of the tuning voltage (VT). Note: In the PLL off mode, the phase comparator output (DO1/2) will be "Hz". When the external low-pass filter (LPF) is used, the external LPF base potential will be unfixed, and the consumption current will increase from the power supply (VDD) through the transistor. In the tuner off state (PLL off mode), fix the phase comparator output (DO1/2) to the "L" level output. Note: The filter circuit constants shown above are for reference only. Examine and design actual circuits according to the system band configuration and your desired characteristics.
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Tin
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DC-DC Converter for VT
This product incorporates the DC-DC converter for the PLL low-pass filter. The DC-DC converter increases voltage by using coil induced electric power. There are two methods for increasing voltage; using the built-in N-channel transistor and using the external transistor. Select either method depending on the voltage to be increased. This product also a VT clamps function to prevent exposure to voltage exceeding a certain limit. The clamp function is helpful for reducing the consumption current and protecting this product.
1. Control Port of DC-DC Converter for VT
Control 1 for DC-DC converter for VT VTDC-DC
Y1 L15(5)
VDET SEL
Y2
0
Y4
VDET ENA
Y8
*
DC-DC for DC-DC converter
Permission of detection voltage input
0: Prohibition 0:
1: 1: Enabled 0 0.75V 0: Detection voltage 0.75 V 1 1.00V 1: Detection voltage 1.00 V
Selection of detection voltage for DC-DC DC-DC converter
Control 2 for DC-DC converter for VT VTDC-DC
Y1 L15(6)
DD0
Y2
DD1
Y4
DD2
Y8
DD3
Selection of clock output frequency for DC-DC converter DC-DC
DD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 A B C D E F
Output frequency Remarks
Clock stop PCTRin 75kHz fosc/2 fosc/4 fosc/8 fosc/16 fosc/32 fXT2 fXT2/2 fXT2/4 fosc/3Note fosc/3 fosc/6 fosc/12 fosc/24 fosc/48
POL=0 DDCK"L"POL=1 DDCK"H""HZ" POL=0 DDCK output "L", POL=1 DDCK output "H" or "HZ"
External clock can be used from the P3-3/PCTRin pin input. (Note) P3-3/PCTRin 75 kHz low-speed oscillator 75kHz clock
Programmable counter clock Note: fosc is the OSCin input clock frequency. foscOSCin
High-speed oscillator clock Note: Enable the high-speed oscillator when it is used.
Programmable counter clock fosc/3POL="0""H""HZ" Note: The duty of fosc/3, or the ratio of the "H" or "HZ" level to the "L" level is 2:1 when POL= POL="1" "L" "0". The ratio is reversed when POL= "1". foscOSCin Note: fosc is the OSCin input clock frequency.
fosc/3 50% PCTRin
Note: Any clocks other than the fosc/3 clock have a duty of 50%. Note: Enable the pulse counter function when using the PCTRin input clock
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Control 3 DC-DC VT for DC-DC converter for VT
Y1 L15(7)
Y2
Y4
POL
Y8
*
DDCK DDCK SEL ENA
Clock output logic setting
0: 0..."H""HZ" output is Negative logic "H" or "HZ" output when the stopped 1: Positive logic
1..."L"
"L" output when the output is stopped
Permission of clock output
0: Prohibition (I/O port function) 0 (I/O )
1 (DC-DC ) 1: Enabled (DC-DC converter output function)
0: Use the DDCK1 pin (internal N-ch transistor) 0DDCK1 ( Nch ) 1: Use the DDCK2 pin (external transistor) 1DDCK2 ()
Selection of clock output pin
The DC-DC converter for VT outputs the double clock using the DDCK1 (also used as pin P8-1) or the DDCK2 (also used as pin P9-2). Setting the DDCK ENA bit to "1" enables the doubler operation. The DDCK SEL bit is used to select the pin to be used. The clamp function is provided to keep the doubled voltage at or below a certain voltage. The clamp is controlled by the doubler detection voltage pin VDET (also used as pin P8-1). The doubled voltage is divided by resistance and the resultant potential is inputted into the VDET pin. When the VDET pin potential becomes lower than 0.75 V or 1.00 V, the doubler clock will operate. When the potential becomes higher than these values, the doubler clock will be stopped. The detection voltage can be selected from 0.75 V and 1.00 V and the detection operation is enabled by setting the VDET ENA bit to "1". The doubler clock can be selected from 15 types. Select a frequency that is a little influence by the tuner beat or other factors. The control port for the DC-DC converter for VT is assigned to data port 5, and is accessed by using the OUT1 instruction with [CN = 4H] specified in the operand. These control bits are reset to "0" after system reset. Note: Set the Y2 bit of the Control 1 for the DC-DC converter for VT (L15 (5)) to "0". Note: When the doubler clock pin (DDCK1/2) and the doubler detection voltage input (VDET) are selected, the I/O port output data and control data of the same pins will be in "don't care" state. Note: The DC-DC converter detection voltage input (VDET ENA bit) must be disabled ("0") in the PLL off mode or when it is not being used; otherwise it will increase the consumption current.
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2. Setting of DC-DC Converter for VT
(1) Example of using the DDCK1 internal doubler transistor The DDCK1 pin includes an N-ch transistor for the DC-DC converter, and it can drive the coil directly. This transistor can withstand 6 V and no voltage over this level is permitted. Usually, the doubler clamp function is used to keep the limit the voltage. Set the POL bit to "0" when the DDCK1 pin is used. Shown below is an example of a DC-DC converter circuit using the DDCK1 pin. The clock output of the DDCK1 pin supplies coil-induced pulses through the diode to increase the voltage. The increased voltage is then supplied to the low-pass filter as the doubled voltage for VT. In the following example, pin P8-2, composed of pins 60, controls the turning the divided resistance on/off. When the doubler is on, the program outputs the I/O port "L" level to turn the resistance division on. When the doubler is off, the output is set to "HZ" (input setting) to disconnect the resistance division. Alternately, you can use the GND rather than the 60-pin connection. However, when the GND connection is used, the current from the VDD power supply is always consumed through the coil and the divided resistance in the doubler off state. This way, this control function prevents the current from being consumed in the doubler system circuit when the doubler is off. Note that this control is unnecessary and the GND connection may be used instead, when the power supply used turns off in the tuner off state or when it doesn't matter if the consumption current is increased in the system.
DC-DC converter voltage for VT + 58 VDET 100 Note 60
0.1uF 10uF
VDB 0.75V
Note Power supply VDD) + 220k 100uH
VLCD DC-DC converter clock for VT
59
DDCK1
39k P8-2(ON:"L"output, OFF:HZ)
Example of internal DC-DC transistor doubler circuit Note: Note: Note: Note: Use the low-VF shot key diode for the diode shown above. Recommended diode: 1SS357 Determine the doubler coil constant depending on the DC-DC converter clock frequency and the doubler current capacity. Connect as required, when the output resistance 100 of the DDCK1 pin shown above or the clock output affects the tuner characteristics. It doesn't matter if a zener diode of 5.5 V or below is used as a substitute for the clamp circuit (VDET). Using the zener diode eliminates the need to use the VDET and doubler on/off control pins. When the clamp circuit is used, operation is stopped if the doubled voltatge exceeds the specified level. If the doubled voltage is supplied exceeding the specified voltage while the voltage of DC-DC converter for VT is supplied, the doubler function operates intermittently and may affect the tuner characteristics. To prevent this, it is recommended that doubler and low-pass filter load capacities that will not exceed the detection voltage be determined during tuner operation. The N-ch transistor buffer gate signal for the DDCK1 pin uses the VLCD (3 V) power supply. This allows stable doubler operation, even if the VDD power supply is reduced. When this product is used as shown above, design the tuner circuit to widen the variable range of the tuning voltage (VT). The filter circuit constants shown above are for reference only. Examine and design the actual circuits according to your desired characteristics.
Note:
Note: Note: Note:
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(2) Example of using the DDCK2 external doubler transistor The DDCK2 pin outputs the DC-DC converter clock in the CMOS type. The external transistor is used to increase the voltage like the DDCK1 pin. The doubled voltage can be set freely by using the external transistor. When the DDCK2 pin is used, set the POL bit to "1". Shown below is an example of a DC-DC converter circuit using the DDCK2 pin. Determine the R1/R2 resistance according to your desired doubled voltage. The P8-0 pin control is the same as for the DDCK1 pin.
Voltage of DC-DC converter for VT VTDC-DC Note 0.01uF Power supply (VDD) VDD)
VLCD VLCD DDCK2 57 58 VDET VTDC-DC Clock of DC-DC converter for VT
100uH
4.7k
+ -
59
0.75V
60
0.1uF 10uF
VDB VDB
P8-2 (ON: "L" output, OFF: P8-2(ON:"L"OFF:HZ) HZ)
+ -
R1
R2
DC-DC Example of external DC-DC transistor doubler circuit
Note: Note: Note: Note:
Determine the doubler coil constant depending on the DC-DC converter clock frequency and the doubler current capacity. It doesn't matter if a zener diode is used as a substitute for the clamp circuit (VDET). Using the zener diode eliminates the need to use the VDET and doubler on/off control pins (P8-2). Add the charge up capacitor for the base input of the external transistor when the doubler capacity is insufficient. When the doubler function is turned off by using pin P8-2, turn it off when the voltage of the DC-DC converter for VT has decreased sufficiently. A high voltage is applied to pin P8-2, and this may cause damage. The prebuffer power supply for the DDCK2 pin output uses a VLCD (3 V) pin power supply, allowing stable doubler operation, even if the VDD power supply is reduced. Note that the VDD power supply level is outputted as the "H" level of the DDCK2 pin output. The filter circuit constants shown above are for reference only. Examine and design actual circuits according to your desired characteristics.
Note:
Note:
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3. Configuration of DC-DC Converter for VT
VLCD VLCD DDCK2 57 P9-2 P9-2 output data POL
75kHz
Selector
PCTRin(P3-3) Counter Counter fXT2() fXT2 (high-speed oscillator) OSCin(fosc)
DDCK ENADDCK SEL
VDB VDB VDET ENA 58 VDET
+ -
DC-DC converter clock DC-DC
DD0 DD3
0.75V 1.00V VDET ENA
DDCK ENADDCK SEL
VLCD VLCD
VDET SEL
59
DDCK1 POL
P8-1 output data P8-1
Note: Comparison voltage for the doubler detection voltage (VDET) is the divided voltage of the VEE constant voltage (1.5 V) pin voltage.
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Electronic Volume
This product incorporates 2-channel 32-step (0 to -78 dB, - dB) electronic volume. This allows digitization of volume control of headphone amplifier and reduction of parts. The electronic volume pins are also used as I/O port 5 and I/O port pin P4-3. Channels can be switched between channels 1 and 2, which support monaural and stereo sound. The attenuation of the electronic volume is in -2 db steps within the range of -0 to -40 db and in -4 db steps in a range of -40 db to -78 db.
1. Electronic Volume Data Port and Control Port
L15(2) Y1 Y2
VR0 VR1
Y4
VR2
Y8
VR3
L15(3) Y1 Y2
VR4 *
Y4
*
Y8
*
Electronic volume data
STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 -dB 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VR4 * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VR3 * 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VR2 * 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VR1 * 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VR0 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Attenua tion
-dB -78dB -74dB -70dB -66dB -62dB -58dB -54dB -50dB -46dB -42dB -40dB -38dB -36dB -34dB -32dB -30dB -28dB -26dB -24dB -22dB -20dB -18dB -16dB -14dB -12dB -10dB -8dB -6dB -4dB -2dB -0dB
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Electronic volume control
Y1 L15(4)
VR CH1
Y2
VR CH2
Y4
Y8
VR -dB MUTE
--dB dB bit
0: Normal operation (Electronic volume data attenuation) 1:1 -dB() - dB (Mute)
0
0: prohibition Permission of - dB bit MUTE-dB control by the MUTE bit 1: Enabled Electronic volume pin setting
CH1 0 1 0 1 CH2 0 0 1 1 Electronic volume I/O I/O port P4-3/ VRout1 P5-0/ VRin1 P5-1/ VRcom I/O I/O port
0: 1:
P5-2/ VRin2
P5-3/ VRout2
I/O I/O port Electronic volume
Electronic volume
The electronic volume pins are also used as port 5 and port P4-3 pins. These pins are switched to electronic volume pins by using the VR CH1 and VR CH2 bits. Set this bit to "1" to use the pin as an electronic volume pin. The electronic volume has two channels. Channel 1 (VR CH1 bit) and Channel 2 (VR CH2 bit); corresponding to VRout1/VRin1 and VRout2/VRin2 pins respectively, and the channels are individually adjustable. The electronic volume attenuation is set by the electronic volume data, which has 5 bits. Setting the most significant bit updates the lower 4 bits of the electronic volume data, meaning the most significant bit must be accessed; even if only the lower bits are changed. The volume can be muted only by setting the -dB bit. When this bit is set to -dB, the electronic volume data will be retained, and the previous attenuation recovered when -dB is released again. Note that the -dB state obtained by setting all the electronic volume data to "0" is the same operation as the state obtained by the -dB bit setting. The electronic volume can also be set to -dB, depending on changes in the I/O port input. When there are changes in the inputs of the I/O port that has been enabled to break and the MUTE bit is set to "1", the volume will be in muted (-dB) state. This is used for quick muting, for example, when band switching. This setting is enabled be setting the VR MUTE bit to "1". This is set by the internal MUTE bit, it is also effective to set the MUTE/P9-1 pin as the I/O port. ( Refer to the sections on MUTE output.) The electronic volume control port is assigned to data port 5, and is accessed by using the OUT1 instruction with [CN = 4H] specified in the operand. The electronic volume control port is reset to "0" after a system reset.
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2. Electronic Volume Configuration and Circuit Example
The electronic volume is configured by connecting the tuner and headphone amplifier as shown below.
44 VRout1
1uF
Tuner
R channel output R
1uF 45
VRin1
L L channel output 1uF
VRcom
46
R channel input R
47
VRin2
1uF
L channel input L
48
VRout2
Reference output Headphone amplifier
Example of electronic volume connection circuit
The electronic volume reference voltage (VRcom) is usually connected to the reference output pin of the headphone amplifier. When the reference output pin is not available, connect this potential to the GND level or the VEE pin (1.5 V constant voltage). If the reference voltage (VRcom) is connected to GND, the distortion factor becomes 0.1% or below when the input level (VRin) is 0.2 Vp-p or below. Caution must be taken as the distortion will be worse when this input level is exceeded. Note: The circuit shown above is for reference only. Examine and design actual circuits according to your desired characteristics.
Volume data
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3. Electronic Volume Configuration
The electronic volume is composed of a decoder, analog switches and resistors and the control circuit. The decoder, analog switches and resistors are powered by the VLCD pin (3 V) power supply, which allows stable operation, even if the VDD pin power supply fluctuates.
VLCD VLCD MUTE VR MUTE -dB
VRout1 44 VRin1 45
32 31 30
30k
Decoder
VR0
0 VRcom 46 1
VR2
VR3
VR4
30k
30 31 32
VRin2
47
VRout2 48
Note: The analog circuit in the electronic volume circuit is powered by the VLCD pin (3 V) power supply. Therefore, up to 3 V can be inputted to VRin1/2. The logic section is powered by the VCPU pin power supply. Note: Volume switching by the zero cross detection is unavailable, hence noise may occur when the attenuation is switched. Note: The VRin1/2 input total resistance is 30 k (typ.). Note: The electronic volume distortion factor is 0.05% at the typical and 0.1% at the maximum (with VRin = 0.4 Vp-p input).
Volume data
1
VR1
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IF Counter
This is a 20-bit general-purpose counter that counts the intermediate frequency (IF) of FM or AM during auto tuning and can be used to detect auto stop signals. It can also measure the VCO of the analog tuner and detect the received frequency.
4. IF Counter Control Ports and Data Ports
IF counter control 1 Y1 Y2 IFin Y4 Prescaller IN Y8 0 0: IFin pin input setting 1: OSCin pin input setting
L16(0)
NC
Setting of OSCin pre-scaler input to IF counter Selection between IF input and input port
0: Input port (IN) setting 1: IF input setting
IF input operating frequency range 0.35 MHz to 12 MHz 0.03 MHz to 1 MHz
Setting of IF input nose cancel circuit 0: Invalid 1: Valid (Noise cancel operation)
Note: When the input port setting is selected, frequency detection can be carried out by CMOS input to the IF counter. Note: When the IF input setting is selected, the IF input amplifier turns off when in the PLL off mode. To use the IF counter in the PLL off mode, select the input port setting (CMOS input). Note: When the counter input is set to the prescaler input, the 1/1516 prescaler is fixed to 16 frequency divisions in the pulse swallow method and this frequency is inputted to the IF counter. Note: For the input frequency range when the prescaler input setting is selected, refer to the section on Programmable counter. Note: Set the Y8 bit of the IF control 1 port (L16 (0)) to "0".
IF counter control 2
Y1
Y2
Y4 G0
Y8 G1
Selection of gate time for frequency measurement (Measurement time) G1 0 0 1 1 G0 0 1 0 1 Gate time 1 ms 4 ms 16 ms 64 ms
L16(1)
STA/ STP MANUAL
Selection of automatic or manual frequency measurement 0: Auto mode (Take measurements during the gate time listed above) 1: Manual mode (Start and stop measurements according to the STA/ STP bit.)
IF counter start/stop control bit 0: Counter stop 1: Counter start Y1 Y2 TA1 Y4 TA2 Y8 TA3
L16(F) 11(F)
TA0
PLL amplifier setting register
Set all "1" (FH)
Note: In the PLL amplifier setting register, the TA0 and TA1 bits are used for setting the OSCin input amplifier, and the TA2 and TA3 bits are used for setting the IFin input amplifier.
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IF monitor Y1 Y2
MANUAL
Y4 OVER
Y8 0 0: IF counter measured value 1: IF counter measured value 0: IF counter automatic mode 1: IF counter manual mode 0: IF counter measurement finished 1: IF counter measuring
K17
BUSY
Overflow detection
< 220 - 1 = > 220 (overflow state) =
Operation mode
Operation monitor
K12
Y1 F0 2
0
K13
Y2 F1 Y4 F2 Y8 F3 Y1 F4 Y2 F5 Y4 F6 Y8 F7
K14
Y1 F8 Y2 F9 Y4 Y8
K15
Y1 Y2 Y4 Y8
K16
Y1 Y2 Y4 Y8
F10 F11
F12 F13 F14 F15
F16 F17 F18 F19 219
LSB
IF counter data
MSB
The IF counter calculates the IF signals usually from the tuner and detects the auto stop signal. When the IFin bit is set to "1", the IFin input amplifier will operate and the IF counter will be enabled. The gain of the input amplifier can be changed by the amplifier setting register port (L16 (F), K11 (F)). Set this register to all "1". In the PLL off mode, this amplifier is disabled and the IFin input becomes high impedance. The IF input frequency range varies depending on the NC bit. When the NC bit is set to "1", the internal noise cancel circuit operates. When the NC bit is "0", the frequency range is 0.35 to 12 MHz. When the NC bit is "1", the noise cancel circuit operates and the frequency range is 0.03 to 1 MHz. Set this bit depending on the IF frequency to be detected. The IF counter has two counting methods; namely the automatic and manual IF counter modes respectively. Counting is carried out using the following methods: (1) Automatic IF counter mode To select the automatic mode for the IF counter, set the MANUAL bit to "0", and specify the gate time depending on the frequency band to be measured. When the STA/ STP bit is set to "1", the IF counter will start operation, the clock will be inputted during the specified gate time, the number of these input pulses will be counted, and the counter will stop the operation. Whether or not the IF counter has finished counting can be checked by referring to 20 the BUSY bit. The OVER bit becomes "1" when there is a pulse input a measured value of 2 or over. The frequency being inputted can be measured by checking that the BUSY and OVER bits are set to"0" and loading the IF data of F0 to F19. Manual IF counter mode Use this mode when the frequency is measured by controlling the gate time using the internal time base (for example, 10 Hz). Set the MANUAL bit to "1" to activate the manual mode. At this time, the gate time setting reverts to "don't care" state. Counting starts by setting the STA/ STP bit to "1". By setting the STA/ STP bit to "0", counting is finished and the data is loaded in binary format.
(2)
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5. IF Counter Configuration
The IF counter is composed of an input amplifier, a gate time control circuit and a 20-bit binary counter. The OSCin prescaler clock can be inputted as the IF counter input.
TA2/3 IFin 0.01 F 49 IFin Prescaler IN Noise Cancel Gate NC VPLL 50 1 kHz Gate time control circuit Manual G0 G1 STA/STP F0~F19 20-bit binary counter OVER OVER
PSC OSCin 0.01 F 51
Amplifi
1/1516 HF TA0/1 Prescaler IN To programmable counter
Note: All the binary counters of the IF counter operate at the rising edge. Note: When the OSCin prescaler clock is counted by the IF counter, 1/1516 is fixed to the 1/16 frequency division by setting the PLL mode to HF mode. The clock is directly inputted when in LF mode. Note: The IF counter input amplifier, the OSCin input amplifier and the programmable counter are powered by the VPLL pin power supply. This power supply level can be supplied regardless of the VDD/VCPU pin power supply level. In PLL off mode, the VPLL pin power supply can be turned off. The IF counter control register and the IF counter power supply use the VCPU pin power supply. Therefore, the contents of the register will be retained after the VPLL pin power supply is turned off. Note: The IFin pin has a built-in amplifier that allows small-amplitude operation by linking to the capacitor. PLL off mode, the IFin input becomes high impedance. In
IF counter input "1" Data set to STA/ STP bit
BUSY bit
1 kHz
Gate
Binary counter input
Example of operation timing in automatic IF counter mode
Note: The IF counter ues the 1 kHz clock. There is a delay of up to 1 ms from the time when the start instruction is executed to the time when the gate opens.
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Test Port
This is the internal port used to test the device functions. These ports are assigned to data port 7 and can be accessed by using the OUT1 instruction with [CN = 6H] specified in the operand. Set all to "0" in the normal program.
L16(2)
L16(3)
Y1 #0
Y2 #1
Y4 #2
Y8 #3
Y1 #4
Y2
Y4
Y8
Test port
Setting the following data to test ports #3 to #0 enables various signals to be output from the MUTE pin.
#3 0 0 0 0 0 #2 0 0 0 0 1 #1 0 0 1 1 0 #0 0 1 0 1 0 Data 0 1 2 3 4 Prohibition MUTE pin output MUTE output Programmable counter frequency Reference frequency 2 Hz
~
~
~
~
1
1
1
1
Note: The MUTE pin is also used for pin P9-1. This pin must be set as the MUTE pin when you need signals to be output from the MUTE pin.
Application to Emulator Chip
When the RESET pin is at the "L" level and pulses are inputted to the TEST pin, various kinds of test modes will be activated and the device will operate as an emulator chip. Three types of test modes are available, and the software development tool can be configured by using three devices. You can confirm the radio operation while developing software by connecting this software development tool to the tuner IC.
~
F
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Absolute Maximum Rating (Ta = 25C)
Characteristics Supply voltage (Note 1) Symbol VDD VO1 VO2 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 PD Topr Tstg
(*) (*) (*) (*) (*) (*) (*) (*)
Rating -0.3 ~ 4.0 -0.3 ~ VDB + 0.3 -0.3 ~ 6.0 -0.3 ~ VLCD + 0.3 -0.3 ~ VCPU + 0.3 -0.3 ~ 6.0 -0.3 ~ VPLL + 0.3 -0.3 ~ VDD + 0.3 -0.3 ~ VDB + 0.3 100 -10 ~ 60 -65 ~ 150
Unit V V V V V V V V V mW C C
Output withstand voltage 1 (Note 2) Output withstand voltage 2 Input voltage 1 Input voltage 2 Input voltage 3 Input voltage 4 Input voltage 5 Input voltage 6 (Note3) (Note3) (Note3) (Note3) (Note3) (Note3) (Note 2)
Power dissipation Operating temperature Storage temperature
Note 1: Note 2: Note 3:
The supply voltage (VDD) indicates the maximum rating of five pins, VDD, VCPU, VDB, VPLL and VLCD. The relationship of the potentials is as follows: VDD VLCD, VDD VDB, VDD VCPU, VCPU VLCD Each output voltage corresponds to the following pin: VO1: I/O port 6 pin, VO2: DDCK1, Tout, I/O port 8 pin Each input voltage corresponds to the following pin: VIN1: All I/O port pins except for those listed below VIN2: RESET pin VIN3: I/O port 8 pin, P9-0 pin VIN4: OSCin and IFin pins VIN5: Xin1 pin VIN6: I/O port 6 and Tin pins
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Electrical Characteristics (Unless otherwise specified, Ta = 25C, VDD = VPLL = 1.5 V, VDB
= VCPU =3.0 V)
Characteristics Symbol VDD Operating supply voltage range (Note 1) VCPU VPLL Memory retention voltage range VHD IDD1 Test Circuit (VDD) (VCPU) (VPLL) PLL operation (VCPU) Backup mode PLL operation, OSCin = 30 MHz During operation of CPU only (PLL off and LCD driver operating) In the hard wait mode (Crystal oscillation only) In the soft wait mode (CPU intermittent operation only) (VDD, VPLL) When the CKSTP instruction is executed (VCPU) VCPU = 1.2 ~ 3.6 V, When the CKSTP instruction is executed (Power supply detectin is set to OFF), VDD off (Power supply detectin is set to ON) Test Condition (*) (*) (*) (*) Min 0.9 1.2 0.9 0.75 Typ. ~ ~ ~ ~ 1.0 Max 1.8 3.6 1.8 3.6 1.5 mA V Unit
IDD2 Operating supply current (Note 2) IDD3
150
300 A
120
IDD4
140
IHD1
0.1
10
Memory retention current IHD2
0.01
0.5
Note 1: Note 2:
Use supply voltage in the range of VDD VLCD, VDD VDB, VDD VCPU and VCPU VLCD. The operating supply current is the total current of the VDD, VCPU and VPLL pin power supplies.
Crystal Oscillator (Xin1, Xout1)
Characteristics Crystal oscillation frequency Crystal oscillation start time Xin1 amplifier feedback resistance Xout1 output resistance Symbol fXT1 tst1 RfXT1 ROUT1 Test Circuit Test Condition (Xin1, Xout1) (Xin1, Xout1) fXT1 = 75 kHz (Xin1 - Xout1) (Xout1) (*) Min 50 Typ. 75 20 100 Max 1.0 200 Unit kHz s M k
High-speed Oscillator (Xin2, Xout2)
Characteristics High-speed oscillation frequency range High-speed oscillation start time Xin2 amplifier feedback resistance Xout2 output resistance Oscillation operating current (Note 3) Symbol fXT2 tst2 RfXT2 ROUT2 IXT2 Test Circuit Test Condition (Xin2, Xout2) (Xin2, Xout2) fXT2 = 300 ~ 600 kHz (Xin2 - Xout2) (Xout2) (Xin2 - Xout2) (*) Min 300 1 Typ. 1 2 50 Max 600 100 4 Unit kHz ms M k A
Note 3: This value increases when high-speed oscillator is used.
*: Guaranteed when VDD = VPLL = 0.9 - 1.8 V, VCPU = 1.2 - 3.6 V, and Ta = -10 to 60C.
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Constant Voltage Output (VEE), Voltage Doubled Output (VLCD)
Characteristics Symbol Test Circuit Test Condition (VDB) GND reference Clamp off, Charge pump voltage (VDB) GND reference Clamp voltage = 2.0 V setting (VDB) GND reference Clamp voltage = 2.5 V setting (VDB) GND reference Clamp voltage = 3.0 V setting (VLCD) GND reference (VDB) When the charge pump pressure is increased Clamp doubled voltage setting error VDB VEE = 1.5 V (VDB) When the switching regulator pressure is increased VEE = 1.5 V Constant voltage VEE (VEE) GND reference (*) 1.46 1.50 0.05 1.54 V Min Typ. VDD x 2 2.0 2.5 3.0 VEE x 2 Max V Unit
VDB1
VDB2 Doubled output VDB3 VDB4 VLCD
0.05 V
Programmable Counter, IF Counter Operating Frequency Range
Characteristics HF mode LF mode Operating frequency range IFin1 IFin2 HF mode LF mode Input amplitude range IFin1 IFin2 Symbol f HF f LF f IF1 f IF2 VHF VLF VIF1 VIF2 RfIN1 RfIN2 Test Circuit Test Condition (OSCin) VIN = 0.1 ~ 0.6 Vp-p (*) (OSCin) VIN = 0.1 ~ 0.6 Vp-p (*) (IFin) VIN = 0.1 ~ 0.6 Vp-p NC = 0 setting (IFin) VIN = 0.1 ~ 0.6 Vp-p NC = 1 setting (*) (*) Min 1.0 0.5 0.35 0.03 0.1 0.1 0.1 0.1 250 250 Typ. ~ ~ ~ ~ ~ ~ ~ ~ 500 500 Max 30 4 12 1 0.6 0.6 0.6 0.6 1000 1000 k k Vp-p MHz Unit
(OSCin) fIN = 1.0 ~ 30 MHz (*) (OSCin) fIN = 0.5 ~ 4 MHz (IFin) fIN = 0.35 ~ 12 MHz NC = 0 setting (IFin) fIN = 0.03 ~ 1 MHz NC = 1 setting (OSCin) (IFin) (*) (*) (*)
Input amplifier feedback resistance
*: Guaranteed when VDD = VPLL = 0.9 - 1.8 V, VCPU = 1.2 - 3.6 V, and Ta = -10 to 60C.
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I/O Ports 1 to 6 (P1-0 to P16-3) , Serial Interface (SCK1/2, RX1/2, SDIO1/2, TX1/2) (Note 4)
Characteristics Symbol Test Circuit Test Condition VDD = 0.9 V, VLCD = 3.0 V, VOH = VDD - 0.2 V (except for I/O ports 6,8 and P9-0) VDD = 0.9 V, VLCD = 3.0 V, VOH = VDD - 0.2 V (except for I/O ports 6,8 and P9-0) VDD = 0.9 ~ 1.8 V, VLCD = 3.0 V, VOL = 0.2 V (except for I/O port 8 and P9-0) VDD = 0.9 ~ 1.8 V, VLCD = 3.0 V, VOL = 0.2 V (P8-0 to P8-3) VDD = 0.9 ~ 1.8 V, VLCD = 3.0 V, VOL = 0.2 V (P9-0) VIH = VDD, VIL = 0 V (except for I/O ports 6,8 and P9-0) VIH = VDB, VIL = 0 V (P6-0 to P6-3) VIH = 5.5 V, VIL = 0 V (P8-0 to P8-3, P9-0) (except for I/O ports 6,8 and P9-0) (P6-0 to P6-3) (P8-0 to P8-3, P9-0) When P3-0 to P3-3 are set to pull-down or pull-up (TEST) when RESET = "L" When SCK1/SCK2 are set to serial clock input VDD x 0.8 VDD x 0.8 VDD x 0.8 0 25 ~ ~ ~ ~ 50 10 VLCD VDB V "L" level Input pull-up/pull-down resistance Input pull-down resistance SCK input frequency VIL R IN1 R IN2 fSIO 5.5 VDD x 0.2 100 200 k k kHz 1.0 A Min Typ. Max Unit
IOH1 "H" level IOH1L
-0.4
-0.8
-0.5
Output current
IOL1
0.4
0.8
mA
"L" level
IOL2
2
4
IOL3
20
Input leak current ILI "H" level Input voltage VIH
Note 4: The electrical characteristics in serial interface conditions are the same as for the I/O ports.
LCD Driver Output (COM1 to COM4 , S1 to S18)
Characteristics "H" level "L" level 1/3 VLCD level Bias voltage 1/2 VLCD level 2/3 VLCD level Symbol IOH4 IOL4 VBS2 VBS3 VBS4 ILCD2 LCD driver operating current (Note 5) ILCD3 Test Circuit Test Condition VLCD = 3.0 V, VOH = VLCD - 0.2 V VLCD = 3.0 V, VOL = 0.2 V VLCD = 3 V, no load, when the 1/3 bias type selected VLCD = 3 V, VEE = 1.5 V, no load, when the 1/2 bias selected VLCD = 3 V, no load, when the 1/3 bias selected No load, when the 1/2 bias selected No load, when the 1/3 bias selected Min 0.85 1.35 1.85 Typ. -0.2 0.5 1.00 1.5 2.00 5 100 Max 1.15 1.65 2.15 A V Unit
Output current
mA
Note 5: This value increases when the LCD driver circuit is used.
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Electronic Volume (VRout1, VRin1, VRcom, VRin2, VRout2)
Characteristics Volume resistance Analog switch ON resistance Attenuation error Symbol RVR RON Test Circuit Test Condition IN ~ GND resistor Analog switch on resistor Min 15 Typ. 30 500 0 Max 60 800 Unit k

dB
ATT
2.0
A/D Converter (ADin1 to ADin4)
Characteristics Analog input voltage range Resolution Total conversion error Analog input leak Symbol VAD VRES Test Circuit Test Condition (ADin1 ~ ADin4) Min 0 Typ. ~ 6 Max VDB Unit V bit LSB

VIH = VDB, VIL = 0 V (ADin1 to ADin4)

1.0 1.0
ILI
0.5
A
Phase Comparator (DO1/OT1/P, DO2/OT2/N)
Characteristics Symbol Test Circuit Test Condition VDB = 3.0 V, VOH = VDB - 0.2 V when the output resistance is off VDB = 3.0 V, VOL = 0.2 V when the output resistance is off (DO1, DO2) (DO1, DO2) (DO1, DO2) (DO1, DO2) VDB = 3.0 V, VTLH = 3.0 V, VTLL = 0 V Min Typ. Max Unit
"H" level Output current "L" level
IOH5
-0.4
-0.8
mA
IOL5

0.4
0.8
100
nA k
ROUT1 Output resistance ROUT2 ROUT3 Tristate leak current ITL

5 50 100
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DC-DC Converter Voltage Doubler for VT (VDET, DDCK1, DDCK2)
Characteristics Doubled voltage range Doubled voltage detection setting error Detection operating current (Note 6) "H" level output current Symbol VOUT Test Circuit Test Condition Min 0 Typ. ~ Max 5.5 Unit V V

(VDET) VEE = 1.5 V (VDET) (DDCK2) VOL = 0.2 V when DDCK2 is selected (DDCK2) VOL = 0.2 V, when DDCK1 is selected (DDCK1) VOL = 0.2 V, when DDCK1 is selected (DDCK1) VIH = 5.5 V, when DDCK1 is selected
VDET
IDET IOH1 IOL1
-0.4
0.4 2
10
0.05 1.0
A
-0.8
0.8 4
mA
"L" level output current IOL2 Output off leak current IOFF
A
Note 6:
This value increases when the tdoubled voltage detection circuit is used.
Transistor for Low-pass Filter (Tout, Tin)
Characteristics "L" level output current Output off leak current Input leak current Symbol IOL3 IOFF ILI Test Circuit Test Condition (Tout) VOL = 0.2 V, Tin = 1.5 V (Tout) VOH = 5.5 V, Tin = 0 V (Tin) VOB = VIH = 3.6 V VIL = 0 V Min Typ. 20 Max Unit mA

1.0 1.0

A A
Reset Signal Input ( RESET )
Characteristics Input leak current "H" level Input voltage "L" level VIL Symbol ILI VIH Test Circuit Test Condition VIH = VCPU, VIL = 0 V Min Typ. Max Unit

VCPU x 0.8 0
~ ~
1.0
VCPU
A

V VCPU x 0.2
Reduced Voltage Detection Circuit
Characteristics Reduced voltage detection setting error Reduced voltage detection operating current (Note 7) Symbol Test Circuit Test Condition (VDD) VEE = 1.5 V Min Typ. Max Unit V
VBL
ILI

20
0.03
A
Note 7:
This value increases when the detection circuit is used.
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Package Dimensions
Weight: 0.32 g (standard)
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